yosys/frontends/verific
Clifford Wolf 84982b3083 Improve naming scheme for (VHDL) modules imported from Verific
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-24 12:13:50 +02:00
..
Makefile.inc Move Verific SVA importer to extra C++ source file 2018-02-18 13:52:49 +01:00
README Fix spelling 2019-03-09 00:43:50 +00:00
example.sby Improve docs for verific bindings, add simply sby example 2017-07-22 11:58:51 +02:00
example.sv Improve docs for verific bindings, add simply sby example 2017-07-22 11:58:51 +02:00
verific.cc Improve naming scheme for (VHDL) modules imported from Verific 2019-10-24 12:13:50 +02:00
verific.h Automatically prune init attributes in verific front-end, fixes #1237 2019-08-07 15:31:49 +02:00
verificsva.cc Use State::S{0,1} 2019-08-06 16:22:47 -07:00

README


This directory contains Verific bindings for Yosys.
See http://www.verific.com/ for details.


Verific Features that should be enabled in your Verific library
===============================================================

database/DBCompileFlags.h:
	DB_PRESERVE_INITIAL_VALUE


Testing Verific+Yosys+SymbiYosys for formal verification
========================================================

Install Yosys+Verific, SymbiYosys, and Yices2. Install instructions:
http://symbiyosys.readthedocs.io/en/latest/quickstart.html#installing

Then run in the following command in this directory:

	sby -f example.sby

This will generate approximately one page of text output. The last lines
should be something like this:

	SBY [example] summary: Elapsed clock time [H:MM:SS (secs)]: 0:00:00 (0)
	SBY [example] summary: Elapsed process time [H:MM:SS (secs)]: 0:00:00 (0)
	SBY [example] summary: engine_0 (smtbmc yices) returned PASS for basecase
	SBY [example] summary: engine_0 (smtbmc yices) returned PASS for induction
	SBY [example] summary: successful proof by k-induction.
	SBY [example] DONE (PASS, rc=0)