mirror of https://github.com/YosysHQ/yosys.git
373 lines
10 KiB
C++
373 lines
10 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2020 David Shah <dave@ds0.me>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct SynthNexusPass : public ScriptPass
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{
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SynthNexusPass() : ScriptPass("synth_nexus", "synthesis for Lattice Nexus FPGAs") { }
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void on_register() override
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{
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RTLIL::constpad["synth_nexus.abc9.W"] = "300";
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}
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" synth_nexus [options]\n");
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log("\n");
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log("This command runs synthesis for Lattice Nexus FPGAs.\n");
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log("\n");
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log(" -top <module>\n");
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log(" use the specified module as top module\n");
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log("\n");
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log(" -family <device>\n");
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log(" run synthesis for the specified Nexus device\n");
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log(" supported values: lifcl, lfd2nx\n");
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log("\n");
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log(" -json <file>\n");
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log(" write the design to the specified JSON file. writing of an output file\n");
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log(" is omitted if this parameter is not specified.\n");
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log("\n");
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log(" -vm <file>\n");
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log(" write the design to the specified structural Verilog file. writing of\n");
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log(" an output file is omitted if this parameter is not specified.\n");
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log("\n");
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log(" -run <from_label>:<to_label>\n");
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log(" only run the commands between the labels (see below). an empty\n");
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log(" from label is synonymous to 'begin', and empty to label is\n");
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log(" synonymous to the end of the command list.\n");
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log("\n");
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log(" -noflatten\n");
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log(" do not flatten design before synthesis\n");
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log("\n");
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log(" -dff\n");
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log(" run 'abc'/'abc9' with -dff option\n");
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log("\n");
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log(" -retime\n");
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log(" run 'abc' with '-dff -D 1' options\n");
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log("\n");
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log(" -noccu2\n");
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log(" do not use CCU2 cells in output netlist\n");
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log("\n");
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log(" -nodffe\n");
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log(" do not use flipflops with CE in output netlist\n");
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log("\n");
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log(" -nobram\n");
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log(" do not use block RAM cells in output netlist\n");
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log("\n");
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log(" -nolutram\n");
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log(" do not use LUT RAM cells in output netlist\n");
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log("\n");
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log(" -nowidelut\n");
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log(" do not use PFU muxes to implement LUTs larger than LUT4s\n");
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log("\n");
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log(" -noiopad\n");
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log(" do not insert IO buffers\n");
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log("\n");
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log(" -abc9\n");
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log(" use new ABC9 flow (EXPERIMENTAL)\n");
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log("\n");
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log("The following commands are executed by this synthesis command:\n");
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help_script();
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log("\n");
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}
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string top_opt, json_file, vm_file, family;
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bool noccu2, nodffe, nobram, nolutram, nowidelut, noiopad, flatten, dff, retime, abc9;
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void clear_flags() override
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{
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top_opt = "-auto-top";
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family = "lifcl";
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json_file = "";
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vm_file = "";
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noccu2 = false;
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nodffe = false;
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nobram = false;
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nolutram = false;
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nowidelut = false;
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noiopad = false;
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flatten = true;
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dff = false;
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retime = false;
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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string run_from, run_to;
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clear_flags();
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-top" && argidx+1 < args.size()) {
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top_opt = "-top " + args[++argidx];
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continue;
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}
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if (args[argidx] == "-json" && argidx+1 < args.size()) {
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json_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-vm" && argidx+1 < args.size()) {
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vm_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-run" && argidx+1 < args.size()) {
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size_t pos = args[argidx+1].find(':');
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if (pos == std::string::npos)
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break;
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run_from = args[++argidx].substr(0, pos);
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run_to = args[argidx].substr(pos+1);
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continue;
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}
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if ((args[argidx] == "-family") && argidx+1 < args.size()) {
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family = args[++argidx];
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continue;
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}
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if (args[argidx] == "-flatten") {
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flatten = true;
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continue;
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}
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if (args[argidx] == "-noflatten") {
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flatten = false;
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continue;
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}
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if (args[argidx] == "-dff") {
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dff = true;
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continue;
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}
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if (args[argidx] == "-retime") {
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retime = true;
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continue;
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}
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if (args[argidx] == "-noccu2") {
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noccu2 = true;
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continue;
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}
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if (args[argidx] == "-nodffe") {
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nodffe = true;
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continue;
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}
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if (args[argidx] == "-nobram") {
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nobram = true;
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continue;
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}
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if (args[argidx] == "-nolutram") {
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nolutram = true;
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continue;
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}
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if (args[argidx] == "-nowidelut") {
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nowidelut = true;
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continue;
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}
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if (args[argidx] == "-noiopad") {
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noiopad = true;
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continue;
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}
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if (args[argidx] == "-abc9") {
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abc9 = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (!design->full_selection())
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log_cmd_error("This command only operates on fully selected designs!\n");
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if (abc9 && retime)
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log_cmd_error("-retime option not currently compatible with -abc9!\n");
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log_header(design, "Executing SYNTH_NEXUS pass.\n");
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log_push();
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run_script(design, run_from, run_to);
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log_pop();
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}
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void script() override
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{
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if (family != "lifcl" && family != "lfd2nx")
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log_cmd_error("Invalid Nexus -family setting: '%s'.\n", family.c_str());
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if (check_label("begin"))
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{
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run("read_verilog -lib -specify +/nexus/cells_sim.v +/nexus/cells_xtra.v");
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run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
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}
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if (check_label("coarse"))
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{
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run("proc");
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if (flatten || help_mode)
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run("flatten");
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run("tribuf -logic");
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run("deminout");
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run("opt_expr");
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run("opt_clean");
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run("check");
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run("opt -nodffe -nosdff");
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run("fsm");
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run("opt");
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run("wreduce");
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run("peepopt");
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run("opt_clean");
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run("share");
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run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
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run("opt_expr");
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run("opt_clean");
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run("alumacc");
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run("opt");
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run("memory -nomap");
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run("opt_clean");
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}
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if (!nobram && check_label("map_bram", "(skip if -nobram)"))
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{
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run("memory_bram -rules +/nexus/brams.txt");
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run("setundef -zero -params t:$__NX_PDP16K");
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run("techmap -map +/nexus/brams_map.v");
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}
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if (!nolutram && check_label("map_lutram", "(skip if -nolutram)"))
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{
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run("memory_bram -rules +/nexus/lutrams.txt");
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run("setundef -zero -params t:$__NEXUS_DPR16X4");
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run("techmap -map +/nexus/lutrams_map.v");
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}
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if (check_label("map_ffram"))
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{
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run("opt -fast -mux_undef -undriven -fine");
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run("memory_map -iattr -attr !ram_block -attr !rom_block -attr logic_block "
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"-attr syn_ramstyle=auto -attr syn_ramstyle=registers "
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"-attr syn_romstyle=auto -attr syn_romstyle=logic");
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run("opt -undriven -fine");
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}
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if (check_label("map_gates"))
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{
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if (noccu2)
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run("techmap");
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else
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run("techmap -map +/techmap.v -map +/nexus/arith_map.v");
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if (help_mode || !noiopad)
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run("iopadmap -bits -outpad OB I:O -inpad IB O:I -toutpad $__NX_TOUTPAD OE:I:O -tinoutpad $__NX_TINOUTPAD OE:O:I:B A:top", "(skip if '-noiopad')");
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run("opt -fast");
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if (retime || help_mode)
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run("abc -dff -D 1", "(only if -retime)");
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}
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if (check_label("map_ffs"))
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{
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run("opt_clean");
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std::string dfflegalize_args = " -cell $_DFF_P_ 01 -cell $_DFF_PP?_ r -cell $_SDFF_PP?_ r -cell $_DLATCH_?_ x";
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if (help_mode) {
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dfflegalize_args += " [-cell $_DFFE_PP_ 01 -cell $_DFFE_PP?P_ r -cell $_SDFFE_PP?P_ r]";
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} else if (!nodffe) {
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dfflegalize_args += " -cell $_DFFE_PP_ 01 -cell $_DFFE_PP?P_ r -cell $_SDFFE_PP?P_ r";
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}
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run("dfflegalize" + dfflegalize_args, "($_*DFFE_* only if not -nodffe)");
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if ((abc9 && dff) || help_mode)
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run("zinit -all w:* t:$_DFF_?_ t:$_DFFE_??_ t:$_SDFF*", "(only if -abc9 and -dff");
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run("techmap -D NO_LUT -map +/nexus/cells_map.v");
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run("opt_expr -undriven -mux_undef");
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run("simplemap");
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run("attrmvcp -copy -attr syn_useioff");
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run("opt_clean");
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}
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if (check_label("map_luts"))
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{
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run("techmap -map +/nexus/latches_map.v");
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if (abc9) {
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std::string abc9_opts;
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if (nowidelut)
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abc9_opts += " -maxlut 4";
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std::string k = "synth_nexus.abc9.W";
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if (active_design && active_design->scratchpad.count(k))
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abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());
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else
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abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str());
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if (nowidelut)
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abc9_opts += " -maxlut 4";
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if (dff)
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abc9_opts += " -dff";
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run("abc9" + abc9_opts);
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} else {
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std::string abc_args = " -dress";
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if (nowidelut)
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abc_args += " -lut 4";
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else
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abc_args += " -lut 4:5";
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if (dff)
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abc_args += " -dff";
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run("abc" + abc_args);
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}
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run("clean");
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}
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if (check_label("map_cells"))
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{
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run("techmap -map +/nexus/cells_map.v");
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// This is needed for Radiant, but perhaps not optimal for nextpnr...
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run("setundef -zero");
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run("hilomap -singleton -hicell VHI Z -locell VLO Z");
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run("clean");
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}
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if (check_label("check"))
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{
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run("autoname");
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run("hierarchy -check");
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run("stat");
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run("check -noinit");
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}
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if (check_label("json"))
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{
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if (!json_file.empty() || help_mode)
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run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
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}
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if (check_label("vm"))
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{
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if (!vm_file.empty() || help_mode)
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run(stringf("write_verilog %s", help_mode ? "<file-name>" : vm_file.c_str()));
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}
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}
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} SynthNexusPass;
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PRIVATE_NAMESPACE_END
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