mirror of https://github.com/YosysHQ/yosys.git
380 lines
8.9 KiB
Verilog
380 lines
8.9 KiB
Verilog
(* abc9_lut=1, lib_whitebox *)
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module LUT4(input A, B, C, D, output Z);
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parameter INIT = "0x0000";
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`include "parse_init.vh"
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localparam initp = parse_init(INIT);
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wire [7:0] s3 = D ? initp[15:8] : initp[7:0];
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wire [3:0] s2 = C ? s3[ 7:4] : s3[3:0];
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wire [1:0] s1 = B ? s2[ 3:2] : s2[1:0];
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assign Z = A ? s1[1] : s1[0];
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// Per-input delay differences are considered 'interconnect'
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// so not known yet
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specify
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(A => Z) = 233;
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(B => Z) = 233;
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(C => Z) = 233;
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(D => Z) = 233;
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endspecify
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endmodule
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// This is a placeholder for ABC9 to extract the area/delay
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// cost of 5-input LUTs and is not intended to be instantiated
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(* abc9_lut=2 *)
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module \$__ABC9_LUT5 (input SEL, D, C, B, A, output Z);
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specify
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(SEL => Z) = 171;
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(D => Z) = 303;
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(C => Z) = 311;
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(B => Z) = 309;
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(A => Z) = 306;
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endspecify
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endmodule
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// Two LUT4s and MUX2
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module WIDEFN9(input A0, B0, C0, D0, A1, B1, C1, D1, SEL, output Z);
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parameter INIT0 = "0x0000";
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parameter INIT1 = "0x0000";
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wire z0, z1;
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LUT4 #(.INIT(INIT0)) lut4_0 (.A(A0), .B(B0), .C(C0), .D(D0), .Z(z0));
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LUT4 #(.INIT(INIT1)) lut4_1 (.A(A1), .B(B1), .C(C1), .D(D1), .Z(z1));
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assign Z = SEL ? z1 : z0;
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endmodule
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(* abc9_box, lib_whitebox *)
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module INV(input A, output Z);
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assign Z = !A;
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specify
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(A => Z) = 10;
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endspecify
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endmodule
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// Bidirectional IO buffer
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module BB(input T, I, output O,
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(* iopad_external_pin *) inout B);
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assign B = T ? 1'bz : O;
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assign I = B;
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endmodule
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// Input buffer
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module IB(
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(* iopad_external_pin *) input I,
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output O);
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assign O = I;
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endmodule
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// Output buffer
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module OB(input I,
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(* iopad_external_pin *) output O);
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assign O = I;
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endmodule
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// Output buffer with tristate
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module OBZ(input I, T,
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(* iopad_external_pin *) output O);
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assign O = T ? 1'bz : I;
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endmodule
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// Constants
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module VLO(output Z);
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assign Z = 1'b0;
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endmodule
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module VHI(output Z);
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assign Z = 1'b1;
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endmodule
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// Vendor flipflops
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// (all have active high clock, enable and set/reset - use INV to invert)
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// Async preset
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(* abc9_box, lib_whitebox *)
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module FD1P3BX(input D, CK, SP, PD, output reg Q);
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parameter GSR = "DISABLED";
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initial Q = 1'b1;
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always @(posedge CK or posedge PD)
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if (PD)
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Q <= 1'b1;
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else if (SP)
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Q <= D;
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specify
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$setup(D, posedge CK, 0);
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$setup(SP, posedge CK, 212);
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$setup(PD, posedge CK, 224);
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`ifndef YOSYS
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if (PD) (posedge CLK => (Q : 1)) = 0;
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`else
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if (PD) (PD => Q) = 0; // Technically, this should be an edge sensitive path
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// but for facilitating a bypass box, let's pretend it's
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// a simple path
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`endif
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if (!PD && SP) (posedge CK => (Q : D)) = 336;
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endspecify
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endmodule
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// Async clear
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(* abc9_box, lib_whitebox *)
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module FD1P3DX(input D, CK, SP, CD, output reg Q);
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parameter GSR = "DISABLED";
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initial Q = 1'b0;
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always @(posedge CK or posedge CD)
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if (CD)
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Q <= 1'b0;
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else if (SP)
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Q <= D;
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specify
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$setup(D, posedge CK, 0);
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$setup(SP, posedge CK, 212);
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$setup(CD, posedge CK, 224);
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`ifndef YOSYS
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if (CD) (posedge CLK => (Q : 0)) = 0;
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`else
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if (CD) (CD => Q) = 0; // Technically, this should be an edge sensitive path
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// but for facilitating a bypass box, let's pretend it's
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// a simple path
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`endif
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if (!CD && SP) (posedge CK => (Q : D)) = 336;
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endspecify
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endmodule
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// Sync clear
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(* abc9_flop, lib_whitebox *)
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module FD1P3IX(input D, CK, SP, CD, output reg Q);
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parameter GSR = "DISABLED";
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initial Q = 1'b0;
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always @(posedge CK)
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if (CD)
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Q <= 1'b0;
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else if (SP)
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Q <= D;
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specify
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$setup(D, posedge CK, 0);
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$setup(SP, posedge CK, 212);
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$setup(CD, posedge CK, 224);
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if (!CD && SP) (posedge CK => (Q : D)) = 336;
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endspecify
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endmodule
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// Sync preset
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(* abc9_flop, lib_whitebox *)
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module FD1P3JX(input D, CK, SP, PD, output reg Q);
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parameter GSR = "DISABLED";
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initial Q = 1'b1;
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always @(posedge CK)
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if (PD)
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Q <= 1'b1;
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else if (SP)
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Q <= D;
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specify
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$setup(D, posedge CK, 0);
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$setup(SP, posedge CK, 212);
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$setup(PD, posedge CK, 224);
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if (!PD && SP) (posedge CK => (Q : D)) = 336;
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endspecify
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endmodule
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// LUT4 with LUT3 tap for CCU2 use only
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(* lib_whitebox *)
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module LUT4_3(input A, B, C, D, output Z, Z3);
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parameter INIT = "0x0000";
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`include "parse_init.vh"
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localparam initp = parse_init(INIT);
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wire [7:0] s3 = D ? initp[15:8] : initp[7:0];
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wire [3:0] s2 = C ? s3[ 7:4] : s3[3:0];
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wire [1:0] s1 = B ? s2[ 3:2] : s2[1:0];
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assign Z = A ? s1[1] : s1[0];
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wire [3:0] s2_3 = C ? initp[ 7:4] : initp[3:0];
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wire [1:0] s1_3 = B ? s2_3[ 3:2] : s2_3[1:0];
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assign Z3 = A ? s1_3[1] : s1_3[0];
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endmodule
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// Carry primitive (incoporating two LUTs)
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(* abc9_box, lib_whitebox *)
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module CCU2(
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(* abc9_carry *) input CIN,
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input A1, B1, C1, D1, A0, B0, C0, D0,
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output S1, S0,
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(* abc9_carry *) output COUT);
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parameter INJECT = "YES";
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parameter INIT0 = "0x0000";
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parameter INIT1 = "0x1111";
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localparam inject_p = (INJECT == "YES") ? 1'b1 : 1'b0;
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wire LUT3_0, LUT4_0, LUT3_1, LUT4_1, carry_0;
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LUT4_3 #(.INIT(INIT0)) lut0 (.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0), .Z3(LUT3_0));
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LUT4_3 #(.INIT(INIT1)) lut1 (.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1), .Z3(LUT3_1));
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assign S0 = LUT4_0 ^ (CIN & ~inject_p);
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assign carry_0 = LUT4_0 ? CIN : (LUT3_0 & ~inject_p);
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assign S1 = LUT4_1 ^ (carry_0 & ~inject_p);
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assign COUT = LUT4_1 ? carry_0 : (LUT3_1 & ~inject_p);
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specify
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(A0 => S0) = 233;
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(B0 => S0) = 233;
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(C0 => S0) = 233;
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(D0 => S0) = 233;
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(CIN => S0) = 228;
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(A0 => S1) = 481;
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(B0 => S1) = 481;
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(C0 => S1) = 481;
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(D0 => S1) = 481;
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(A1 => S1) = 233;
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(B1 => S1) = 233;
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(C1 => S1) = 233;
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(D1 => S1) = 233;
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(CIN => S1) = 307;
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(A0 => COUT) = 347;
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(B0 => COUT) = 347;
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(C0 => COUT) = 347;
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(D0 => COUT) = 347;
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(A1 => COUT) = 347;
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(B1 => COUT) = 347;
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(C1 => COUT) = 347;
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(D1 => COUT) = 347;
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(CIN => COUT) = 59;
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endspecify
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endmodule
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// Packed flipflop
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module OXIDE_FF(input CLK, LSR, CE, DI, M, output reg Q);
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parameter GSR = "ENABLED";
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parameter [127:0] CEMUX = "1";
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parameter CLKMUX = "CLK";
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parameter LSRMUX = "LSR";
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parameter REGDDR = "DISABLED";
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parameter SRMODE = "LSR_OVER_CE";
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parameter REGSET = "RESET";
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parameter [127:0] LSRMODE = "LSR";
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wire muxce;
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generate
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case (CEMUX)
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"1": assign muxce = 1'b1;
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"0": assign muxce = 1'b0;
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"INV": assign muxce = ~CE;
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default: assign muxce = CE;
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endcase
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endgenerate
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wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
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wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
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wire srval;
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generate
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if (LSRMODE == "PRLD")
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assign srval = M;
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else
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assign srval = (REGSET == "SET") ? 1'b1 : 1'b0;
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endgenerate
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initial Q = srval;
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generate
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if (REGDDR == "ENABLED") begin
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if (SRMODE == "ASYNC") begin
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always @(posedge muxclk, negedge muxclk, posedge muxlsr)
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if (muxlsr)
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Q <= srval;
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else if (muxce)
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Q <= DI;
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end else begin
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always @(posedge muxclk, negedge muxclk)
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if (muxlsr)
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Q <= srval;
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else if (muxce)
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Q <= DI;
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end
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end else begin
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if (SRMODE == "ASYNC") begin
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always @(posedge muxclk, posedge muxlsr)
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if (muxlsr)
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Q <= srval;
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else if (muxce)
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Q <= DI;
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end else begin
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always @(posedge muxclk)
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if (muxlsr)
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Q <= srval;
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else if (muxce)
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Q <= DI;
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end
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end
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endgenerate
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endmodule
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// Packed combinational logic (for post-pnr sim)
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module OXIDE_COMB(
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input A, B, C, D, // LUT inputs
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input SEL, // mux select input
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input F1, // output from LUT 1 for mux
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input FCI, // carry input
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input WAD0, WAD1, WAD2, WAD3, // LUTRAM write address inputs
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input WD, // LUTRAM write data input
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input WCK, WRE, // LUTRAM write clock and enable
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output F, // LUT/carry output
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output OFX // mux output
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);
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parameter MODE = "LOGIC"; // LOGIC, CCU2, DPRAM
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parameter [15:0] INIT = 16'h0000;
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parameter INJECT = "YES";
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localparam inject_p = (INJECT == "YES") ? 1'b1 : 1'b0;
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reg [15:0] lut = INIT;
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wire [7:0] s3 = D ? INIT[15:8] : INIT[7:0];
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wire [3:0] s2 = C ? s3[ 7:4] : s3[3:0];
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wire [1:0] s1 = B ? s2[ 3:2] : s2[1:0];
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wire Z = A ? s1[1] : s1[0];
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wire [3:0] s2_3 = C ? INIT[ 7:4] : INIT[3:0];
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wire [1:0] s1_3 = B ? s2_3[ 3:2] : s2_3[1:0];
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wire Z3 = A ? s1_3[1] : s1_3[0];
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generate
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if (MODE == "DPRAM") begin
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always @(posedge WCK)
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if (WRE)
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lut[{WAD3, WAD2, WAD1, WAD0}] <= WD;
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end
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if (MODE == "CCU2") begin
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assign F = Z ^ (FCI & ~inject_p);
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assign FCO = Z ? FCI : (Z3 & ~inject_p);
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end else begin
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assign F = Z;
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end
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endgenerate
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assign OFX = SEL ? F1 : F;
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endmodule
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// LUTRAM
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module DPR16X4(
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input [3:0] RAD, DI, WAD,
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input WRE, WCK,
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output [3:0] DO
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);
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parameter INITVAL = "0x0000000000000000";
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`include "parse_init.vh"
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localparam [63:0] parsed_init = parse_init_64(INITVAL);
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reg [3:0] mem[0:15];
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integer i;
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initial begin
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for (i = 0; i < 15; i++)
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mem[i] = parsed_init[i * 4 +: 4];
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end
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always @(posedge WCK)
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if (WRE)
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mem[WAD] <= DI;
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assign DO = mem[RAD];
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endmodule
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