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Eddie Hung e7ef7fa443 Reverse bits in INIT parameter for Xilinx, since MSB is shifted first 2019-03-14 09:38:42 -07:00
..
tests Improved xilinx "bram1" test 2015-04-09 17:12:12 +02:00
.gitignore Added support for initialized xilinx brams 2015-04-06 17:07:10 +02:00
Makefile.inc Changes required for VPR place and route synth_xilinx. 2019-03-01 12:02:27 -08:00
arith_map.v Changes required for VPR place and route synth_xilinx. 2019-03-01 12:02:27 -08:00
brams.txt Added read-enable to memory model 2015-09-25 12:23:11 +02:00
brams_bb.v Added Xilinx bram black-box modules 2015-04-06 08:44:30 +02:00
brams_init.py Squelch trailing whitespace, including meta-whitespace 2018-03-11 16:03:41 +01:00
brams_map.v Revert BRAM WRITE_MODE changes. 2019-03-04 09:22:22 -08:00
cells_map.v Reverse bits in INIT parameter for Xilinx, since MSB is shifted first 2019-03-14 09:38:42 -07:00
cells_sim.v Merge remote-tracking branch 'origin/master' into xc7srl 2019-03-14 08:59:19 -07:00
cells_xtra.sh Merge remote-tracking branch 'origin/master' into xc7srl 2019-03-14 08:59:19 -07:00
cells_xtra.v Merge remote-tracking branch 'origin/master' into xc7srl 2019-03-14 08:59:19 -07:00
drams.txt Added memory_bram "make_outreg" feature 2015-04-09 16:08:54 +02:00
drams_map.v Xilinx DRAMS: RAM64X1D, RAM128X1D 2015-04-09 13:37:07 +02:00
ff_map.v Changes required for VPR place and route synth_xilinx. 2019-03-01 12:02:27 -08:00
lut_map.v Changes required for VPR place and route synth_xilinx. 2019-03-01 12:02:27 -08:00
synth_xilinx.cc Misspell 2019-03-14 09:06:56 -07:00