mirror of https://github.com/YosysHQ/yosys.git
505 lines
15 KiB
C++
505 lines
15 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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#include "kernel/hashlib.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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static void rename_in_module(RTLIL::Module *module, std::string from_name, std::string to_name, bool flag_output)
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{
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from_name = RTLIL::escape_id(from_name);
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to_name = RTLIL::escape_id(to_name);
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if (module->count_id(to_name))
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log_cmd_error("There is already an object `%s' in module `%s'.\n", to_name.c_str(), module->name.c_str());
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RTLIL::Wire *wire_to_rename = module->wire(from_name);
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RTLIL::Cell *cell_to_rename = module->cell(from_name);
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if (wire_to_rename != nullptr) {
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log("Renaming wire %s to %s in module %s.\n", log_id(wire_to_rename), log_id(to_name), log_id(module));
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module->rename(wire_to_rename, to_name);
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if (wire_to_rename->port_id || flag_output) {
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if (flag_output)
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wire_to_rename->port_output = true;
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module->fixup_ports();
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}
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return;
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}
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if (cell_to_rename != nullptr) {
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if (flag_output)
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log_cmd_error("Called with -output but the specified object is a cell.\n");
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log("Renaming cell %s to %s in module %s.\n", log_id(cell_to_rename), log_id(to_name), log_id(module));
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module->rename(cell_to_rename, to_name);
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return;
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}
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log_cmd_error("Object `%s' not found!\n", from_name.c_str());
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}
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static std::string derive_name_from_src(const std::string &src, int counter)
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{
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std::string src_base = src.substr(0, src.find('|'));
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if (src_base.empty())
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return stringf("$%d", counter);
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else
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return stringf("\\%s$%d", src_base.c_str(), counter);
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}
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static IdString derive_name_from_cell_output_wire(const RTLIL::Cell *cell, string suffix)
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{
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// Find output
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const SigSpec *output = nullptr;
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int num_outputs = 0;
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for (auto &connection : cell->connections()) {
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if (cell->output(connection.first)) {
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output = &connection.second;
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num_outputs++;
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}
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}
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if (num_outputs != 1) // Skip cells thad drive multiple outputs
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return cell->name;
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std::string name = "";
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for (auto &chunk : output->chunks()) {
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// Skip cells that drive privately named wires
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if (!chunk.wire || chunk.wire->name.str()[0] == '$')
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return cell->name;
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if (name != "")
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name += "$";
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name += chunk.wire->name.str();
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if (chunk.wire->width != chunk.width) {
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name += "[";
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if (chunk.width != 1)
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name += std::to_string(chunk.offset + chunk.width) + ":";
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name += std::to_string(chunk.offset) + "]";
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}
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}
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if (suffix.empty()) {
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suffix = cell->type.str();
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}
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return name + suffix;
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}
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static bool rename_witness(RTLIL::Design *design, dict<RTLIL::Module *, int> &cache, RTLIL::Module *module)
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{
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auto cached = cache.find(module);
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if (cached != cache.end()) {
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if (cached->second == -1)
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log_error("Cannot rename witness signals in a design containing recursive instantiations.\n");
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return cached->second;
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}
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cache.emplace(module, -1);
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bool has_witness_signals = false;
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for (auto cell : module->cells())
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{
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RTLIL::Module *impl = design->module(cell->type);
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if (impl != nullptr) {
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bool witness_in_cell = rename_witness(design, cache, impl);
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has_witness_signals |= witness_in_cell;
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if (witness_in_cell && !cell->name.isPublic()) {
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std::string name = cell->name.c_str() + 1;
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for (auto &c : name)
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if ((c < 'a' || c > 'z') && (c < 'A' || c > 'Z') && (c < '0' || c > '9') && c != '_')
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c = '_';
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auto new_id = module->uniquify("\\_witness_." + name);
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cell->set_hdlname_attribute({ "_witness_", strstr(new_id.c_str(), ".") + 1 });
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module->rename(cell, new_id);
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}
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}
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if (cell->type.in(ID($anyconst), ID($anyseq), ID($anyinit), ID($allconst), ID($allseq))) {
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has_witness_signals = true;
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auto QY = cell->type == ID($anyinit) ? ID::Q : ID::Y;
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auto sig_out = cell->getPort(QY);
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for (auto chunk : sig_out.chunks()) {
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if (chunk.is_wire() && !chunk.wire->name.isPublic()) {
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std::string name = stringf("%s_%s", cell->type.c_str() + 1, cell->name.c_str() + 1);
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for (auto &c : name)
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if ((c < 'a' || c > 'z') && (c < 'A' || c > 'Z') && (c < '0' || c > '9') && c != '_')
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c = '_';
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auto new_id = module->uniquify("\\_witness_." + name);
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auto new_wire = module->addWire(new_id, GetSize(sig_out));
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new_wire->set_hdlname_attribute({ "_witness_", strstr(new_id.c_str(), ".") + 1 });
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module->connect({sig_out, new_wire});
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cell->setPort(QY, new_wire);
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break;
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}
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}
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}
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}
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cache[module] = has_witness_signals;
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return has_witness_signals;
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}
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struct RenamePass : public Pass {
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RenamePass() : Pass("rename", "rename object in the design") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" rename old_name new_name\n");
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log("\n");
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log("Rename the specified object. Note that selection patterns are not supported\n");
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log("by this command.\n");
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log("\n");
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log("\n");
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log("\n");
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log(" rename -output old_name new_name\n");
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log("\n");
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log("Like above, but also make the wire an output. This will fail if the object is\n");
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log("not a wire.\n");
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log("\n");
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log("\n");
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log(" rename -src [selection]\n");
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log("\n");
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log("Assign names auto-generated from the src attribute to all selected wires and\n");
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log("cells with private names.\n");
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log("\n");
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log("\n");
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log(" rename -wire [selection] [-suffix <suffix>]\n");
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log("\n");
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log("Assign auto-generated names based on the wires they drive to all selected\n");
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log("cells with private names. Ignores cells driving privatly named wires.\n");
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log("By default, the cell is named after the wire with the cell type as suffix.\n");
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log("The -suffix option can be used to set the suffix to the given string instead.\n");
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log("\n");
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log("\n");
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log(" rename -enumerate [-pattern <pattern>] [selection]\n");
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log("\n");
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log("Assign short auto-generated names to all selected wires and cells with private\n");
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log("names. The -pattern option can be used to set the pattern for the new names.\n");
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log("The character %% in the pattern is replaced with a integer number. The default\n");
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log("pattern is '_%%_'.\n");
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log("\n");
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log("\n");
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log(" rename -witness\n");
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log("\n");
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log("Assigns auto-generated names to all $any*/$all* output wires and containing\n");
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log("cells that do not have a public name. This ensures that, during formal\n");
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log("verification, a solver-found trace can be fully specified using a public\n");
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log("hierarchical names.\n");
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log("\n");
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log("\n");
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log(" rename -hide [selection]\n");
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log("\n");
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log("Assign private names (the ones with $-prefix) to all selected wires and cells\n");
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log("with public names. This ignores all selected ports.\n");
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log("\n");
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log("\n");
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log(" rename -top new_name\n");
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log("\n");
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log("Rename top module.\n");
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log("\n");
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log("\n");
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log(" rename -scramble-name [-seed <seed>] [selection]\n");
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log("\n");
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log("Assign randomly-generated names to all selected wires and cells. The seed option\n");
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log("can be used to change the random number generator seed from the default, but it\n");
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log("must be non-zero.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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std::string pattern_prefix = "_", pattern_suffix = "_";
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std::string cell_suffix = "";
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bool flag_src = false;
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bool flag_wire = false;
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bool flag_enumerate = false;
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bool flag_witness = false;
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bool flag_hide = false;
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bool flag_top = false;
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bool flag_output = false;
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bool flag_scramble_name = false;
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bool got_mode = false;
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unsigned int seed = 1;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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std::string arg = args[argidx];
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if (arg == "-src" && !got_mode) {
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flag_src = true;
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got_mode = true;
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continue;
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}
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if (arg == "-output" && !got_mode) {
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flag_output = true;
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got_mode = true;
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continue;
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}
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if (arg == "-wire" && !got_mode) {
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flag_wire = true;
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got_mode = true;
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continue;
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}
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if (arg == "-enumerate" && !got_mode) {
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flag_enumerate = true;
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got_mode = true;
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continue;
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}
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if (arg == "-witness" && !got_mode) {
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flag_witness = true;
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got_mode = true;
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continue;
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}
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if (arg == "-hide" && !got_mode) {
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flag_hide = true;
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got_mode = true;
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continue;
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}
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if (arg == "-top" && !got_mode) {
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flag_top = true;
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got_mode = true;
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continue;
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}
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if (arg == "-scramble-name" && !got_mode) {
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flag_scramble_name = true;
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got_mode = true;
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continue;
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}
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if (arg == "-pattern" && argidx+1 < args.size() && args[argidx+1].find('%') != std::string::npos) {
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int pos = args[++argidx].find('%');
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pattern_prefix = args[argidx].substr(0, pos);
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pattern_suffix = args[argidx].substr(pos+1);
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continue;
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}
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if (arg == "-suffix" && argidx + 1 < args.size()) {
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cell_suffix = args[++argidx];
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continue;
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}
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if (arg == "-seed" && argidx+1 < args.size()) {
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seed = std::stoi(args[++argidx]);
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continue;
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}
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break;
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}
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if (flag_src)
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{
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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{
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int counter = 0;
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dict<RTLIL::Wire *, IdString> new_wire_names;
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dict<RTLIL::Cell *, IdString> new_cell_names;
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for (auto wire : module->selected_wires())
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if (wire->name[0] == '$')
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new_wire_names.emplace(wire, derive_name_from_src(wire->get_src_attribute(), counter++));
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for (auto cell : module->selected_cells())
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if (cell->name[0] == '$')
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new_cell_names.emplace(cell, derive_name_from_src(cell->get_src_attribute(), counter++));
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for (auto &it : new_wire_names)
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module->rename(it.first, it.second);
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for (auto &it : new_cell_names)
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module->rename(it.first, it.second);
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}
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}
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else
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if (flag_wire)
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{
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules()) {
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dict<RTLIL::Cell *, IdString> new_cell_names;
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for (auto cell : module->selected_cells())
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if (cell->name[0] == '$')
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new_cell_names[cell] = derive_name_from_cell_output_wire(cell, cell_suffix);
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for (auto &it : new_cell_names)
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module->rename(it.first, it.second);
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}
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}
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else
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if (flag_enumerate)
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{
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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{
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int counter = 0;
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dict<RTLIL::Wire *, IdString> new_wire_names;
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dict<RTLIL::Cell *, IdString> new_cell_names;
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for (auto wire : module->selected_wires())
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if (wire->name[0] == '$') {
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RTLIL::IdString buf;
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do buf = stringf("\\%s%d%s", pattern_prefix.c_str(), counter++, pattern_suffix.c_str());
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while (module->wire(buf) != nullptr);
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new_wire_names[wire] = buf;
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}
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for (auto cell : module->selected_cells())
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if (cell->name[0] == '$') {
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RTLIL::IdString buf;
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do buf = stringf("\\%s%d%s", pattern_prefix.c_str(), counter++, pattern_suffix.c_str());
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while (module->cell(buf) != nullptr);
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new_cell_names[cell] = buf;
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}
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for (auto &it : new_wire_names)
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module->rename(it.first, it.second);
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for (auto &it : new_cell_names)
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module->rename(it.first, it.second);
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}
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}
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else
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if (flag_witness)
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{
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extra_args(args, argidx, design, false);
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RTLIL::Module *module = design->top_module();
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if (module == nullptr)
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log_cmd_error("No top module found!\n");
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dict<RTLIL::Module *, int> cache;
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rename_witness(design, cache, module);
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}
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else
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if (flag_hide)
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{
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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{
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dict<RTLIL::Wire *, IdString> new_wire_names;
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dict<RTLIL::Cell *, IdString> new_cell_names;
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for (auto wire : module->selected_wires())
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if (wire->name.isPublic() && wire->port_id == 0)
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new_wire_names[wire] = NEW_ID;
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for (auto cell : module->selected_cells())
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if (cell->name.isPublic())
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new_cell_names[cell] = NEW_ID;
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for (auto &it : new_wire_names)
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module->rename(it.first, it.second);
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for (auto &it : new_cell_names)
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module->rename(it.first, it.second);
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}
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}
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else
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if (flag_top)
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{
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if (argidx+1 != args.size())
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log_cmd_error("Invalid number of arguments!\n");
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IdString new_name = RTLIL::escape_id(args[argidx]);
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RTLIL::Module *module = design->top_module();
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if (module == nullptr)
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log_cmd_error("No top module found!\n");
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log("Renaming module %s to %s.\n", log_id(module), log_id(new_name));
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design->rename(module, new_name);
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}
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else
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if (flag_scramble_name)
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{
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extra_args(args, argidx, design);
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if (seed == 0)
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log_error("Seed for -scramble-name cannot be zero.\n");
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for (auto module : design->selected_modules())
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{
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if (module->memories.size() != 0 || module->processes.size() != 0) {
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log_warning("Skipping module %s with unprocessed memories or processes\n", log_id(module));
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continue;
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}
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dict<RTLIL::Wire *, IdString> new_wire_names;
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dict<RTLIL::Cell *, IdString> new_cell_names;
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for (auto wire : module->selected_wires())
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if (wire->port_id == 0) {
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seed = mkhash_xorshift(seed);
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new_wire_names[wire] = stringf("$_%u_", seed);
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}
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for (auto cell : module->selected_cells()) {
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seed = mkhash_xorshift(seed);
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new_cell_names[cell] = stringf("$_%u_", seed);
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}
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for (auto &it : new_wire_names)
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module->rename(it.first, it.second);
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for (auto &it : new_cell_names)
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module->rename(it.first, it.second);
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}
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}
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else
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{
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if (argidx+2 != args.size())
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log_cmd_error("Invalid number of arguments!\n");
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std::string from_name = args[argidx++];
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std::string to_name = args[argidx++];
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if (!design->selected_active_module.empty())
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{
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if (design->module(design->selected_active_module) != nullptr)
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rename_in_module(design->module(design->selected_active_module), from_name, to_name, flag_output);
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}
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else
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{
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if (flag_output)
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log_cmd_error("Mode -output requires that there is an active module selected.\n");
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RTLIL::Module *module_to_rename = nullptr;
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for (auto module : design->modules())
|
|
if (module->name == from_name || RTLIL::unescape_id(module->name) == from_name) {
|
|
module_to_rename = module;
|
|
break;
|
|
}
|
|
|
|
if (module_to_rename != nullptr) {
|
|
to_name = RTLIL::escape_id(to_name);
|
|
log("Renaming module %s to %s.\n", module_to_rename->name.c_str(), to_name.c_str());
|
|
design->rename(module_to_rename, to_name);
|
|
} else
|
|
log_cmd_error("Object `%s' not found!\n", from_name.c_str());
|
|
}
|
|
}
|
|
}
|
|
} RenamePass;
|
|
|
|
PRIVATE_NAMESPACE_END
|