mirror of https://github.com/YosysHQ/yosys.git
313 lines
6.8 KiB
Verilog
313 lines
6.8 KiB
Verilog
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// ============================================================================
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// LCU
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(* techmap_celltype = "$lcu" *)
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module _80_xilinx_lcu (P, G, CI, CO);
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parameter WIDTH = 2;
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(* force_downto *)
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input [WIDTH-1:0] P, G;
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input CI;
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(* force_downto *)
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output [WIDTH-1:0] CO;
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wire _TECHMAP_FAIL_ = WIDTH <= 2;
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genvar i;
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`ifdef _EXPLICIT_CARRY
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localparam EXPLICIT_CARRY = 1'b1;
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`else
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localparam EXPLICIT_CARRY = 1'b0;
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`endif
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generate if (EXPLICIT_CARRY || `LUT_SIZE == 4) begin
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(* force_downto *)
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wire [WIDTH-1:0] C = {CO, CI};
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(* force_downto *)
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wire [WIDTH-1:0] S = P & ~G;
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generate for (i = 0; i < WIDTH; i = i + 1) begin:slice
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MUXCY muxcy (
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.CI(C[i]),
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.DI(G[i]),
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.S(S[i]),
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.O(CO[i])
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);
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end endgenerate
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end else begin
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localparam CARRY4_COUNT = (WIDTH + 3) / 4;
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localparam MAX_WIDTH = CARRY4_COUNT * 4;
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localparam PAD_WIDTH = MAX_WIDTH - WIDTH;
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(* force_downto *)
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wire [MAX_WIDTH-1:0] S = {{PAD_WIDTH{1'b0}}, P & ~G};
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(* force_downto *)
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wire [MAX_WIDTH-1:0] GG = {{PAD_WIDTH{1'b0}}, G};
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(* force_downto *)
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wire [MAX_WIDTH-1:0] C;
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assign CO = C;
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generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice
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if (i == 0) begin
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CARRY4 carry4
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(
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.CYINIT(CI),
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.CI (1'd0),
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.DI (GG[i*4 +: 4]),
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.S (S [i*4 +: 4]),
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.CO (C [i*4 +: 4]),
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);
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end else begin
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CARRY4 carry4
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(
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.CYINIT(1'd0),
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.CI (C [i*4 - 1]),
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.DI (GG[i*4 +: 4]),
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.S (S [i*4 +: 4]),
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.CO (C [i*4 +: 4]),
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);
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end
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end endgenerate
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end endgenerate
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endmodule
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// ============================================================================
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// ALU
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(* techmap_celltype = "$alu" *)
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module _80_xilinx_alu (A, B, CI, BI, X, Y, CO);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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parameter _TECHMAP_CONSTVAL_CI_ = 0;
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parameter _TECHMAP_CONSTMSK_CI_ = 0;
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(* force_downto *)
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input [A_WIDTH-1:0] A;
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(* force_downto *)
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input [B_WIDTH-1:0] B;
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(* force_downto *)
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output [Y_WIDTH-1:0] X, Y;
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input CI, BI;
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(* force_downto *)
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output [Y_WIDTH-1:0] CO;
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wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
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(* force_downto *)
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wire [Y_WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
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(* force_downto *)
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wire [Y_WIDTH-1:0] AA = A_buf;
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(* force_downto *)
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wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
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genvar i;
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`ifdef _EXPLICIT_CARRY
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localparam EXPLICIT_CARRY = 1'b1;
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`else
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localparam EXPLICIT_CARRY = 1'b0;
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`endif
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generate if (`LUT_SIZE == 4) begin
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(* force_downto *)
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wire [Y_WIDTH-1:0] C = {CO, CI};
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(* force_downto *)
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wire [Y_WIDTH-1:0] S = {AA ^ BB};
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genvar i;
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generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
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MUXCY muxcy (
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.CI(C[i]),
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.DI(AA[i]),
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.S(S[i]),
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.O(CO[i])
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);
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XORCY xorcy (
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.CI(C[i]),
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.LI(S[i]),
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.O(Y[i])
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);
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end endgenerate
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end else if (EXPLICIT_CARRY) begin
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(* force_downto *)
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wire [Y_WIDTH-1:0] S = AA ^ BB;
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wire CINIT;
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// Carry chain.
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//
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// VPR requires that the carry chain never hit the fabric. The CO input
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// to this techmap is the carry outputs for synthesis, e.g. might hit the
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// fabric.
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//
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// So we maintain two wire sets, CO_CHAIN is the carry that is for VPR,
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// e.g. off fabric dedicated chain. CO is the carry outputs that are
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// available to the fabric.
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(* force_downto *)
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wire [Y_WIDTH-1:0] CO_CHAIN;
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(* force_downto *)
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wire [Y_WIDTH-1:0] C = {CO_CHAIN, CINIT};
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// If carry chain is being initialized to a constant, techmap the constant
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// source. Otherwise techmap the fabric source.
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generate for (i = 0; i < 1; i = i + 1) begin:slice
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CARRY0 #(.CYINIT_FABRIC(1)) carry(
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.CI_INIT(CI),
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.DI(AA[0]),
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.S(S[0]),
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.CO_CHAIN(CO_CHAIN[0]),
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.CO_FABRIC(CO[0]),
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.O(Y[0])
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);
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end endgenerate
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generate for (i = 1; i < Y_WIDTH-1; i = i + 1) begin:slice
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if(i % 4 == 0) begin
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CARRY0 carry (
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.CI(C[i]),
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.DI(AA[i]),
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.S(S[i]),
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.CO_CHAIN(CO_CHAIN[i]),
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.CO_FABRIC(CO[i]),
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.O(Y[i])
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);
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end
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else
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begin
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CARRY carry (
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.CI(C[i]),
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.DI(AA[i]),
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.S(S[i]),
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.CO_CHAIN(CO_CHAIN[i]),
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.CO_FABRIC(CO[i]),
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.O(Y[i])
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);
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end
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end endgenerate
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generate for (i = Y_WIDTH-1; i < Y_WIDTH; i = i + 1) begin:slice
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if(i % 4 == 0) begin
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CARRY0 top_of_carry (
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.CI(C[i]),
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.DI(AA[i]),
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.S(S[i]),
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.CO_CHAIN(CO_CHAIN[i]),
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.O(Y[i])
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);
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end
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else
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begin
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CARRY top_of_carry (
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.CI(C[i]),
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.DI(AA[i]),
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.S(S[i]),
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.CO_CHAIN(CO_CHAIN[i]),
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.O(Y[i])
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);
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end
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// Turns out CO_FABRIC and O both use [ABCD]MUX, so provide
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// a non-congested path to output the top of the carry chain.
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// Registering the output of the CARRY block would solve this, but not
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// all designs do that.
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if((i+1) % 4 == 0) begin
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CARRY0 carry_output (
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.CI(CO_CHAIN[i]),
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.DI(0),
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.S(0),
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.O(CO[i])
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);
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end
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else
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begin
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CARRY carry_output (
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.CI(CO_CHAIN[i]),
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.DI(0),
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.S(0),
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.O(CO[i])
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);
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end
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end endgenerate
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end else begin
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localparam CARRY4_COUNT = (Y_WIDTH + 3) / 4;
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localparam MAX_WIDTH = CARRY4_COUNT * 4;
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localparam PAD_WIDTH = MAX_WIDTH - Y_WIDTH;
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(* force_downto *)
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wire [MAX_WIDTH-1:0] S = {{PAD_WIDTH{1'b0}}, AA ^ BB};
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(* force_downto *)
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wire [MAX_WIDTH-1:0] DI = {{PAD_WIDTH{1'b0}}, AA};
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(* force_downto *)
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wire [MAX_WIDTH-1:0] O;
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(* force_downto *)
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wire [MAX_WIDTH-1:0] C;
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assign Y = O, CO = C;
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genvar i;
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generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice
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if (i == 0) begin
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CARRY4 carry4
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(
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.CYINIT(CI),
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.CI (1'd0),
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.DI (DI[i*4 +: 4]),
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.S (S [i*4 +: 4]),
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.O (O [i*4 +: 4]),
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.CO (C [i*4 +: 4])
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);
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end else begin
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CARRY4 carry4
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(
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.CYINIT(1'd0),
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.CI (C [i*4 - 1]),
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.DI (DI[i*4 +: 4]),
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.S (S [i*4 +: 4]),
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.O (O [i*4 +: 4]),
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.CO (C [i*4 +: 4])
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);
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end
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end endgenerate
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end endgenerate
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assign X = S;
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endmodule
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