mirror of https://github.com/YosysHQ/yosys.git
964 lines
29 KiB
C++
964 lines
29 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2014 Clifford Wolf <clifford@clifford.at>
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* Copyright (C) 2014 Johann Glaser <Johann.Glaser@gmx.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/satgen.h"
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#include "kernel/consteval.h"
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#include "kernel/celledges.h"
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#include "kernel/macc.h"
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#include <algorithm>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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static uint32_t xorshift32_state = 123456789;
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static uint32_t xorshift32(uint32_t limit) {
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xorshift32_state ^= xorshift32_state << 13;
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xorshift32_state ^= xorshift32_state >> 17;
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xorshift32_state ^= xorshift32_state << 5;
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return xorshift32_state % limit;
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}
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static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, std::string cell_type_flags, bool constmode, bool muxdiv)
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{
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RTLIL::Module *module = design->addModule(ID(gold));
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RTLIL::Cell *cell = module->addCell(ID(UUT), cell_type);
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RTLIL::Wire *wire;
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if (cell_type.in(ID($mux), ID($pmux)))
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{
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int width = 1 + xorshift32(8);
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int swidth = cell_type == ID($mux) ? 1 : 1 + xorshift32(8);
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wire = module->addWire(ID::A);
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wire->width = width;
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wire->port_input = true;
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cell->setPort(ID::A, wire);
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wire = module->addWire(ID::B);
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wire->width = width * swidth;
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wire->port_input = true;
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cell->setPort(ID::B, wire);
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wire = module->addWire(ID::S);
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wire->width = swidth;
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wire->port_input = true;
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cell->setPort(ID::S, wire);
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wire = module->addWire(ID::Y);
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wire->width = width;
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wire->port_output = true;
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cell->setPort(ID::Y, wire);
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}
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if (cell_type == ID($fa))
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{
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int width = 1 + xorshift32(8);
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wire = module->addWire(ID::A);
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wire->width = width;
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wire->port_input = true;
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cell->setPort(ID::A, wire);
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wire = module->addWire(ID::B);
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wire->width = width;
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wire->port_input = true;
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cell->setPort(ID::B, wire);
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wire = module->addWire(ID::C);
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wire->width = width;
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wire->port_input = true;
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cell->setPort(ID::C, wire);
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wire = module->addWire(ID::X);
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wire->width = width;
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wire->port_output = true;
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cell->setPort(ID::X, wire);
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wire = module->addWire(ID::Y);
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wire->width = width;
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wire->port_output = true;
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cell->setPort(ID::Y, wire);
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}
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if (cell_type == ID($lcu))
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{
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int width = 1 + xorshift32(8);
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wire = module->addWire(ID::P);
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wire->width = width;
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wire->port_input = true;
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cell->setPort(ID::P, wire);
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wire = module->addWire(ID::G);
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wire->width = width;
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wire->port_input = true;
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cell->setPort(ID::G, wire);
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wire = module->addWire(ID::CI);
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wire->port_input = true;
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cell->setPort(ID::CI, wire);
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wire = module->addWire(ID::CO);
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wire->width = width;
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wire->port_output = true;
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cell->setPort(ID::CO, wire);
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}
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if (cell_type == ID($macc))
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{
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Macc macc;
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int width = 1 + xorshift32(8);
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int depth = 1 + xorshift32(6);
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int mulbits_a = 0, mulbits_b = 0;
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RTLIL::Wire *wire_a = module->addWire(ID::A);
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wire_a->width = 0;
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wire_a->port_input = true;
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for (int i = 0; i < depth; i++)
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{
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int size_a = xorshift32(width) + 1;
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int size_b = depth > 4 ? 0 : xorshift32(width) + 1;
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if (mulbits_a + size_a*size_b <= 96 && mulbits_b + size_a + size_b <= 16 && xorshift32(2) == 1) {
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mulbits_a += size_a * size_b;
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mulbits_b += size_a + size_b;
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} else
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size_b = 0;
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Macc::port_t this_port;
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wire_a->width += size_a;
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this_port.in_a = RTLIL::SigSpec(wire_a, wire_a->width - size_a, size_a);
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wire_a->width += size_b;
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this_port.in_b = RTLIL::SigSpec(wire_a, wire_a->width - size_b, size_b);
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this_port.is_signed = xorshift32(2) == 1;
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this_port.do_subtract = xorshift32(2) == 1;
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macc.ports.push_back(this_port);
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}
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wire = module->addWire(ID::B);
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wire->width = xorshift32(mulbits_a ? xorshift32(4)+1 : xorshift32(16)+1);
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wire->port_input = true;
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macc.bit_ports = wire;
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wire = module->addWire(ID::Y);
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wire->width = width;
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wire->port_output = true;
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cell->setPort(ID::Y, wire);
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macc.to_cell(cell);
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}
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if (cell_type == ID($lut))
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{
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int width = 1 + xorshift32(6);
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wire = module->addWire(ID::A);
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wire->width = width;
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wire->port_input = true;
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cell->setPort(ID::A, wire);
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wire = module->addWire(ID::Y);
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wire->port_output = true;
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cell->setPort(ID::Y, wire);
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RTLIL::SigSpec config;
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for (int i = 0; i < (1 << width); i++)
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config.append(xorshift32(2) ? State::S1 : State::S0);
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cell->setParam(ID::LUT, config.as_const());
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}
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if (cell_type == ID($sop))
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{
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int width = 1 + xorshift32(8);
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int depth = 1 + xorshift32(8);
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wire = module->addWire(ID::A);
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wire->width = width;
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wire->port_input = true;
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cell->setPort(ID::A, wire);
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wire = module->addWire(ID::Y);
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wire->port_output = true;
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cell->setPort(ID::Y, wire);
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RTLIL::SigSpec config;
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for (int i = 0; i < width*depth; i++)
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switch (xorshift32(3)) {
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case 0:
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config.append(State::S1);
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config.append(State::S0);
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break;
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case 1:
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config.append(State::S0);
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config.append(State::S1);
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break;
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case 2:
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config.append(State::S0);
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config.append(State::S0);
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break;
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}
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cell->setParam(ID::DEPTH, depth);
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cell->setParam(ID::TABLE, config.as_const());
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}
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if (cell_type_flags.find('A') != std::string::npos) {
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wire = module->addWire(ID::A);
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wire->width = 1 + xorshift32(8);
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wire->port_input = true;
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cell->setPort(ID::A, wire);
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}
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if (cell_type_flags.find('B') != std::string::npos) {
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wire = module->addWire(ID::B);
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if (cell_type_flags.find('h') != std::string::npos)
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wire->width = 1 + xorshift32(6);
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else
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wire->width = 1 + xorshift32(8);
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wire->port_input = true;
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cell->setPort(ID::B, wire);
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}
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if (cell_type_flags.find('S') != std::string::npos && xorshift32(2)) {
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if (cell_type_flags.find('A') != std::string::npos)
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cell->parameters[ID::A_SIGNED] = true;
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if (cell_type_flags.find('B') != std::string::npos)
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cell->parameters[ID::B_SIGNED] = true;
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}
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if (cell_type_flags.find('s') != std::string::npos) {
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if (cell_type_flags.find('A') != std::string::npos && xorshift32(2))
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cell->parameters[ID::A_SIGNED] = true;
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if (cell_type_flags.find('B') != std::string::npos && xorshift32(2))
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cell->parameters[ID::B_SIGNED] = true;
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}
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if (cell_type_flags.find('Y') != std::string::npos) {
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wire = module->addWire(ID::Y);
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wire->width = 1 + xorshift32(8);
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wire->port_output = true;
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cell->setPort(ID::Y, wire);
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}
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if (muxdiv && cell_type.in(ID($div), ID($mod))) {
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auto b_not_zero = module->ReduceBool(NEW_ID, cell->getPort(ID::B));
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auto div_out = module->addWire(NEW_ID, GetSize(cell->getPort(ID::Y)));
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module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(div_out)), div_out, b_not_zero, cell->getPort(ID::Y));
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cell->setPort(ID::Y, div_out);
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}
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if (cell_type == ID($alu))
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{
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wire = module->addWire(ID::CI);
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wire->port_input = true;
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cell->setPort(ID::CI, wire);
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wire = module->addWire(ID::BI);
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wire->port_input = true;
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cell->setPort(ID::BI, wire);
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wire = module->addWire(ID::X);
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wire->width = GetSize(cell->getPort(ID::Y));
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wire->port_output = true;
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cell->setPort(ID::X, wire);
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wire = module->addWire(ID::CO);
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wire->width = GetSize(cell->getPort(ID::Y));
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wire->port_output = true;
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cell->setPort(ID::CO, wire);
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}
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if (constmode)
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{
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auto conn_list = cell->connections();
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for (auto &conn : conn_list)
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{
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RTLIL::SigSpec sig = conn.second;
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if (GetSize(sig) == 0 || sig[0].wire == nullptr || sig[0].wire->port_output)
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continue;
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int n, m;
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switch (xorshift32(5))
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{
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case 0:
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n = xorshift32(GetSize(sig) + 1);
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for (int i = 0; i < n; i++)
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sig[i] = xorshift32(2) == 1 ? State::S1 : State::S0;
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break;
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case 1:
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n = xorshift32(GetSize(sig) + 1);
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for (int i = n; i < GetSize(sig); i++)
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sig[i] = xorshift32(2) == 1 ? State::S1 : State::S0;
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break;
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case 2:
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n = xorshift32(GetSize(sig));
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m = xorshift32(GetSize(sig));
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for (int i = min(n, m); i < max(n, m); i++)
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sig[i] = xorshift32(2) == 1 ? State::S1 : State::S0;
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break;
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}
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cell->setPort(conn.first, sig);
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}
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}
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module->fixup_ports();
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cell->fixup_parameters();
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cell->check();
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}
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static void run_edges_test(RTLIL::Design *design, bool verbose)
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{
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Module *module = *design->modules().begin();
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Cell *cell = *module->cells().begin();
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ezSatPtr ezptr;
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ezSAT &ez = *ezptr.get();
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SigMap sigmap(module);
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SatGen satgen(&ez, &sigmap);
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FwdCellEdgesDatabase edges_db(sigmap);
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if (!edges_db.add_edges_from_cell(cell))
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log_error("Creating edge database failed for this cell!\n");
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dict<SigBit, pool<SigBit>> satgen_db;
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satgen.setContext(&sigmap, "X:");
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satgen.importCell(cell);
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satgen.setContext(&sigmap, "Y:");
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satgen.importCell(cell);
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vector<tuple<SigBit, int, int>> input_db, output_db;
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for (auto &conn : cell->connections())
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{
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SigSpec bits = sigmap(conn.second);
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satgen.setContext(&sigmap, "X:");
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std::vector<int> xbits = satgen.importSigSpec(bits);
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satgen.setContext(&sigmap, "Y:");
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std::vector<int> ybits = satgen.importSigSpec(bits);
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for (int i = 0; i < GetSize(bits); i++)
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if (cell->input(conn.first))
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input_db.emplace_back(bits[i], xbits[i], ybits[i]);
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else
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output_db.emplace_back(bits[i], xbits[i], ybits[i]);
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}
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if (verbose)
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log("\nSAT solving for all edges:\n");
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for (int i = 0; i < GetSize(input_db); i++)
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{
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SigBit inbit = std::get<0>(input_db[i]);
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if (verbose)
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log(" Testing input signal %s:\n", log_signal(inbit));
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vector<int> xinbits, yinbits;
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for (int k = 0; k < GetSize(input_db); k++)
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if (k != i) {
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xinbits.push_back(std::get<1>(input_db[k]));
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yinbits.push_back(std::get<2>(input_db[k]));
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}
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int xyinbit_ok = ez.vec_eq(xinbits, yinbits);
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for (int k = 0; k < GetSize(output_db); k++)
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{
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SigBit outbit = std::get<0>(output_db[k]);
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int xoutbit = std::get<1>(output_db[k]);
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int youtbit = std::get<2>(output_db[k]);
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bool is_edge = ez.solve(xyinbit_ok, ez.XOR(xoutbit, youtbit));
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if (is_edge)
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satgen_db[inbit].insert(outbit);
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if (verbose) {
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bool is_ref_edge = edges_db.db.count(inbit) && edges_db.db.at(inbit).count(outbit);
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log(" %c %s %s\n", is_edge ? 'x' : 'o', log_signal(outbit), is_edge == is_ref_edge ? "OK" : "ERROR");
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}
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}
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}
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if (satgen_db == edges_db.db)
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log("PASS.\n");
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else
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log_error("SAT-based edge table does not match the database!\n");
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}
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static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::string uut_name, std::ofstream &vlog_file)
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{
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log("Eval testing:%c", verbose ? '\n' : ' ');
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RTLIL::Module *gold_mod = design->module(ID(gold));
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RTLIL::Module *gate_mod = design->module(ID(gate));
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ConstEval gold_ce(gold_mod), gate_ce(gate_mod);
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ezSatPtr ez1, ez2;
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SigMap sigmap(gold_mod);
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SatGen satgen1(ez1.get(), &sigmap);
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SatGen satgen2(ez2.get(), &sigmap);
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satgen2.model_undef = true;
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if (!nosat)
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for (auto cell : gold_mod->cells()) {
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satgen1.importCell(cell);
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satgen2.importCell(cell);
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}
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if (vlog_file.is_open())
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{
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vlog_file << stringf("\nmodule %s;\n", uut_name.c_str());
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for (auto port : gold_mod->ports) {
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RTLIL::Wire *wire = gold_mod->wire(port);
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if (wire->port_input)
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vlog_file << stringf(" reg [%d:0] %s;\n", GetSize(wire)-1, log_id(wire));
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else
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vlog_file << stringf(" wire [%d:0] %s_expr, %s_noexpr;\n", GetSize(wire)-1, log_id(wire), log_id(wire));
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}
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vlog_file << stringf(" %s_expr uut_expr(", uut_name.c_str());
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for (int i = 0; i < GetSize(gold_mod->ports); i++)
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vlog_file << stringf("%s.%s(%s%s)", i ? ", " : "", log_id(gold_mod->ports[i]), log_id(gold_mod->ports[i]),
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gold_mod->wire(gold_mod->ports[i])->port_input ? "" : "_expr");
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vlog_file << stringf(");\n");
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vlog_file << stringf(" %s_expr uut_noexpr(", uut_name.c_str());
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for (int i = 0; i < GetSize(gold_mod->ports); i++)
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vlog_file << stringf("%s.%s(%s%s)", i ? ", " : "", log_id(gold_mod->ports[i]), log_id(gold_mod->ports[i]),
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gold_mod->wire(gold_mod->ports[i])->port_input ? "" : "_noexpr");
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vlog_file << stringf(");\n");
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vlog_file << stringf(" task run;\n");
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vlog_file << stringf(" begin\n");
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vlog_file << stringf(" $display(\"%s\");\n", uut_name.c_str());
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}
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for (int i = 0; i < 64; i++)
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{
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log(verbose ? "\n" : ".");
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gold_ce.clear();
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gate_ce.clear();
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RTLIL::SigSpec in_sig, in_val;
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RTLIL::SigSpec out_sig, out_val;
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std::string vlog_pattern_info;
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for (auto port : gold_mod->ports)
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{
|
|
RTLIL::Wire *gold_wire = gold_mod->wire(port);
|
|
RTLIL::Wire *gate_wire = gate_mod->wire(port);
|
|
|
|
log_assert(gold_wire != nullptr);
|
|
log_assert(gate_wire != nullptr);
|
|
log_assert(gold_wire->port_input == gate_wire->port_input);
|
|
log_assert(GetSize(gold_wire) == GetSize(gate_wire));
|
|
|
|
if (!gold_wire->port_input)
|
|
continue;
|
|
|
|
RTLIL::Const in_value;
|
|
for (int i = 0; i < GetSize(gold_wire); i++)
|
|
in_value.bits.push_back(xorshift32(2) ? State::S1 : State::S0);
|
|
|
|
if (xorshift32(4) == 0) {
|
|
int inv_chance = 1 + xorshift32(8);
|
|
for (int i = 0; i < GetSize(gold_wire); i++)
|
|
if (xorshift32(inv_chance) == 0)
|
|
in_value.bits[i] = RTLIL::Sx;
|
|
}
|
|
|
|
if (verbose)
|
|
log("%s: %s\n", log_id(gold_wire), log_signal(in_value));
|
|
|
|
in_sig.append(gold_wire);
|
|
in_val.append(in_value);
|
|
|
|
gold_ce.set(gold_wire, in_value);
|
|
gate_ce.set(gate_wire, in_value);
|
|
|
|
if (vlog_file.is_open() && GetSize(in_value) > 0) {
|
|
vlog_file << stringf(" %s = 'b%s;\n", log_id(gold_wire), in_value.as_string().c_str());
|
|
if (!vlog_pattern_info.empty())
|
|
vlog_pattern_info += " ";
|
|
vlog_pattern_info += stringf("%s=%s", log_id(gold_wire), log_signal(in_value));
|
|
}
|
|
}
|
|
|
|
if (vlog_file.is_open())
|
|
vlog_file << stringf(" #1;\n");
|
|
|
|
for (auto port : gold_mod->ports)
|
|
{
|
|
RTLIL::Wire *gold_wire = gold_mod->wire(port);
|
|
RTLIL::Wire *gate_wire = gate_mod->wire(port);
|
|
|
|
log_assert(gold_wire != nullptr);
|
|
log_assert(gate_wire != nullptr);
|
|
log_assert(gold_wire->port_output == gate_wire->port_output);
|
|
log_assert(GetSize(gold_wire) == GetSize(gate_wire));
|
|
|
|
if (!gold_wire->port_output)
|
|
continue;
|
|
|
|
RTLIL::SigSpec gold_outval(gold_wire);
|
|
RTLIL::SigSpec gate_outval(gate_wire);
|
|
|
|
if (!gold_ce.eval(gold_outval))
|
|
log_error("Failed to eval %s in gold module.\n", log_id(gold_wire));
|
|
|
|
if (!gate_ce.eval(gate_outval))
|
|
log_error("Failed to eval %s in gate module.\n", log_id(gate_wire));
|
|
|
|
bool gold_gate_mismatch = false;
|
|
for (int i = 0; i < GetSize(gold_wire); i++) {
|
|
if (gold_outval[i] == RTLIL::Sx)
|
|
continue;
|
|
if (gold_outval[i] == gate_outval[i])
|
|
continue;
|
|
gold_gate_mismatch = true;
|
|
break;
|
|
}
|
|
|
|
if (gold_gate_mismatch)
|
|
log_error("Mismatch in output %s: gold:%s != gate:%s\n", log_id(gate_wire), log_signal(gold_outval), log_signal(gate_outval));
|
|
|
|
if (verbose)
|
|
log("%s: %s\n", log_id(gold_wire), log_signal(gold_outval));
|
|
|
|
out_sig.append(gold_wire);
|
|
out_val.append(gold_outval);
|
|
|
|
if (vlog_file.is_open()) {
|
|
vlog_file << stringf(" $display(\"[%s] %s expected: %%b, expr: %%b, noexpr: %%b\", %d'b%s, %s_expr, %s_noexpr);\n",
|
|
vlog_pattern_info.c_str(), log_id(gold_wire), GetSize(gold_outval), gold_outval.as_string().c_str(), log_id(gold_wire), log_id(gold_wire));
|
|
vlog_file << stringf(" if (%s_expr !== %d'b%s) begin $display(\"ERROR\"); $finish; end\n", log_id(gold_wire), GetSize(gold_outval), gold_outval.as_string().c_str());
|
|
vlog_file << stringf(" if (%s_noexpr !== %d'b%s) begin $display(\"ERROR\"); $finish; end\n", log_id(gold_wire), GetSize(gold_outval), gold_outval.as_string().c_str());
|
|
}
|
|
}
|
|
|
|
if (verbose)
|
|
log("EVAL: %s\n", out_val.as_string().c_str());
|
|
|
|
if (!nosat)
|
|
{
|
|
std::vector<int> sat1_in_sig = satgen1.importSigSpec(in_sig);
|
|
std::vector<int> sat1_in_val = satgen1.importSigSpec(in_val);
|
|
|
|
std::vector<int> sat1_model = satgen1.importSigSpec(out_sig);
|
|
std::vector<bool> sat1_model_value;
|
|
|
|
if (!ez1->solve(sat1_model, sat1_model_value, ez1->vec_eq(sat1_in_sig, sat1_in_val)))
|
|
log_error("Evaluating sat model 1 (no undef modeling) failed!\n");
|
|
|
|
if (verbose) {
|
|
log("SAT 1: ");
|
|
for (int i = GetSize(out_sig)-1; i >= 0; i--)
|
|
log("%c", sat1_model_value.at(i) ? '1' : '0');
|
|
log("\n");
|
|
}
|
|
|
|
for (int i = 0; i < GetSize(out_sig); i++) {
|
|
if (out_val[i] != State::S0 && out_val[i] != State::S1)
|
|
continue;
|
|
if (out_val[i] == State::S0 && sat1_model_value.at(i) == false)
|
|
continue;
|
|
if (out_val[i] == State::S1 && sat1_model_value.at(i) == true)
|
|
continue;
|
|
log_error("Mismatch in sat model 1 (no undef modeling) output!\n");
|
|
}
|
|
|
|
std::vector<int> sat2_in_def_sig = satgen2.importDefSigSpec(in_sig);
|
|
std::vector<int> sat2_in_def_val = satgen2.importDefSigSpec(in_val);
|
|
|
|
std::vector<int> sat2_in_undef_sig = satgen2.importUndefSigSpec(in_sig);
|
|
std::vector<int> sat2_in_undef_val = satgen2.importUndefSigSpec(in_val);
|
|
|
|
std::vector<int> sat2_model_def_sig = satgen2.importDefSigSpec(out_sig);
|
|
std::vector<int> sat2_model_undef_sig = satgen2.importUndefSigSpec(out_sig);
|
|
|
|
std::vector<int> sat2_model;
|
|
sat2_model.insert(sat2_model.end(), sat2_model_def_sig.begin(), sat2_model_def_sig.end());
|
|
sat2_model.insert(sat2_model.end(), sat2_model_undef_sig.begin(), sat2_model_undef_sig.end());
|
|
|
|
std::vector<bool> sat2_model_value;
|
|
|
|
if (!ez2->solve(sat2_model, sat2_model_value, ez2->vec_eq(sat2_in_def_sig, sat2_in_def_val), ez2->vec_eq(sat2_in_undef_sig, sat2_in_undef_val)))
|
|
log_error("Evaluating sat model 2 (undef modeling) failed!\n");
|
|
|
|
if (verbose) {
|
|
log("SAT 2: ");
|
|
for (int i = GetSize(out_sig)-1; i >= 0; i--)
|
|
log("%c", sat2_model_value.at(GetSize(out_sig) + i) ? 'x' : sat2_model_value.at(i) ? '1' : '0');
|
|
log("\n");
|
|
}
|
|
|
|
for (int i = 0; i < GetSize(out_sig); i++) {
|
|
if (sat2_model_value.at(GetSize(out_sig) + i)) {
|
|
if (out_val[i] != State::S0 && out_val[i] != State::S1)
|
|
continue;
|
|
} else {
|
|
if (out_val[i] == State::S0 && sat2_model_value.at(i) == false)
|
|
continue;
|
|
if (out_val[i] == State::S1 && sat2_model_value.at(i) == true)
|
|
continue;
|
|
}
|
|
log_error("Mismatch in sat model 2 (undef modeling) output!\n");
|
|
}
|
|
}
|
|
}
|
|
|
|
if (vlog_file.is_open()) {
|
|
vlog_file << stringf(" end\n");
|
|
vlog_file << stringf(" endtask\n");
|
|
vlog_file << stringf("endmodule\n");
|
|
}
|
|
|
|
if (!verbose)
|
|
log(" ok.\n");
|
|
}
|
|
|
|
struct TestCellPass : public Pass {
|
|
TestCellPass() : Pass("test_cell", "automatically test the implementation of a cell type") { }
|
|
void help() YS_OVERRIDE
|
|
{
|
|
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
|
log("\n");
|
|
log(" test_cell [options] {cell-types}\n");
|
|
log("\n");
|
|
log("Tests the internal implementation of the given cell type (for example '$add')\n");
|
|
log("by comparing SAT solver, EVAL and TECHMAP implementations of the cell types..\n");
|
|
log("\n");
|
|
log("Run with 'all' instead of a cell type to run the test on all supported\n");
|
|
log("cell types. Use for example 'all /$add' for all cell types except $add.\n");
|
|
log("\n");
|
|
log(" -n {integer}\n");
|
|
log(" create this number of cell instances and test them (default = 100).\n");
|
|
log("\n");
|
|
log(" -s {positive_integer}\n");
|
|
log(" use this value as rng seed value (default = unix time).\n");
|
|
log("\n");
|
|
log(" -f {ilang_file}\n");
|
|
log(" don't generate circuits. instead load the specified ilang file.\n");
|
|
log("\n");
|
|
log(" -w {filename_prefix}\n");
|
|
log(" don't test anything. just generate the circuits and write them\n");
|
|
log(" to ilang files with the specified prefix\n");
|
|
log("\n");
|
|
log(" -map {filename}\n");
|
|
log(" pass this option to techmap.\n");
|
|
log("\n");
|
|
log(" -simlib\n");
|
|
log(" use \"techmap -D SIMLIB_NOCHECKS -map +/simlib.v -max_iter 2 -autoproc\"\n");
|
|
log("\n");
|
|
log(" -aigmap\n");
|
|
log(" instead of calling \"techmap\", call \"aigmap\"\n");
|
|
log("\n");
|
|
log(" -muxdiv\n");
|
|
log(" when creating test benches with dividers, create an additional mux\n");
|
|
log(" to mask out the division-by-zero case\n");
|
|
log("\n");
|
|
log(" -script {script_file}\n");
|
|
log(" instead of calling \"techmap\", call \"script {script_file}\".\n");
|
|
log("\n");
|
|
log(" -const\n");
|
|
log(" set some input bits to random constant values\n");
|
|
log("\n");
|
|
log(" -nosat\n");
|
|
log(" do not check SAT model or run SAT equivalence checking\n");
|
|
log("\n");
|
|
log(" -noeval\n");
|
|
log(" do not check const-eval models\n");
|
|
log("\n");
|
|
log(" -edges\n");
|
|
log(" test cell edges db creator against sat-based implementation\n");
|
|
log("\n");
|
|
log(" -v\n");
|
|
log(" print additional debug information to the console\n");
|
|
log("\n");
|
|
log(" -vlog {filename}\n");
|
|
log(" create a Verilog test bench to test simlib and write_verilog\n");
|
|
log("\n");
|
|
}
|
|
void execute(std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE
|
|
{
|
|
int num_iter = 100;
|
|
std::string techmap_cmd = "techmap -assert";
|
|
std::string ilang_file, write_prefix;
|
|
xorshift32_state = 0;
|
|
std::ofstream vlog_file;
|
|
bool muxdiv = false;
|
|
bool verbose = false;
|
|
bool constmode = false;
|
|
bool nosat = false;
|
|
bool noeval = false;
|
|
bool edges = false;
|
|
|
|
int argidx;
|
|
for (argidx = 1; argidx < GetSize(args); argidx++)
|
|
{
|
|
if (args[argidx] == "-n" && argidx+1 < GetSize(args)) {
|
|
num_iter = atoi(args[++argidx].c_str());
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-s" && argidx+1 < GetSize(args)) {
|
|
xorshift32_state = atoi(args[++argidx].c_str());
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-map" && argidx+1 < GetSize(args)) {
|
|
techmap_cmd += " -map " + args[++argidx];
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-f" && argidx+1 < GetSize(args)) {
|
|
ilang_file = args[++argidx];
|
|
num_iter = 1;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-w" && argidx+1 < GetSize(args)) {
|
|
write_prefix = args[++argidx];
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-script" && argidx+1 < GetSize(args)) {
|
|
techmap_cmd = "script " + args[++argidx];
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-simlib") {
|
|
techmap_cmd = "techmap -D SIMLIB_NOCHECKS -map +/simlib.v -max_iter 2 -autoproc";
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-aigmap") {
|
|
techmap_cmd = "aigmap";
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-muxdiv") {
|
|
muxdiv = true;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-const") {
|
|
constmode = true;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-nosat") {
|
|
nosat = true;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-noeval") {
|
|
noeval = true;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-edges") {
|
|
edges = true;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-v") {
|
|
verbose = true;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-vlog" && argidx+1 < GetSize(args)) {
|
|
vlog_file.open(args[++argidx], std::ios_base::trunc);
|
|
if (!vlog_file.is_open())
|
|
log_cmd_error("Failed to open output file `%s'.\n", args[argidx].c_str());
|
|
continue;
|
|
}
|
|
break;
|
|
}
|
|
|
|
if (xorshift32_state == 0) {
|
|
xorshift32_state = time(NULL) & 0x7fffffff;
|
|
log("Rng seed value: %d\n", int(xorshift32_state));
|
|
}
|
|
|
|
std::map<IdString, std::string> cell_types;
|
|
std::vector<IdString> selected_cell_types;
|
|
|
|
cell_types[ID($not)] = "ASY";
|
|
cell_types[ID($pos)] = "ASY";
|
|
cell_types[ID($neg)] = "ASY";
|
|
|
|
cell_types[ID($and)] = "ABSY";
|
|
cell_types[ID($or)] = "ABSY";
|
|
cell_types[ID($xor)] = "ABSY";
|
|
cell_types[ID($xnor)] = "ABSY";
|
|
|
|
cell_types[ID($reduce_and)] = "ASY";
|
|
cell_types[ID($reduce_or)] = "ASY";
|
|
cell_types[ID($reduce_xor)] = "ASY";
|
|
cell_types[ID($reduce_xnor)] = "ASY";
|
|
cell_types[ID($reduce_bool)] = "ASY";
|
|
|
|
cell_types[ID($shl)] = "ABshY";
|
|
cell_types[ID($shr)] = "ABshY";
|
|
cell_types[ID($sshl)] = "ABshY";
|
|
cell_types[ID($sshr)] = "ABshY";
|
|
cell_types[ID($shift)] = "ABshY";
|
|
cell_types[ID($shiftx)] = "ABshY";
|
|
|
|
cell_types[ID($lt)] = "ABSY";
|
|
cell_types[ID($le)] = "ABSY";
|
|
cell_types[ID($eq)] = "ABSY";
|
|
cell_types[ID($ne)] = "ABSY";
|
|
// cell_types[ID($eqx)] = "ABSY";
|
|
// cell_types[ID($nex)] = "ABSY";
|
|
cell_types[ID($ge)] = "ABSY";
|
|
cell_types[ID($gt)] = "ABSY";
|
|
|
|
cell_types[ID($add)] = "ABSY";
|
|
cell_types[ID($sub)] = "ABSY";
|
|
cell_types[ID($mul)] = "ABSY";
|
|
cell_types[ID($div)] = "ABSY";
|
|
cell_types[ID($mod)] = "ABSY";
|
|
// cell_types[ID($pow)] = "ABsY";
|
|
|
|
cell_types[ID($logic_not)] = "ASY";
|
|
cell_types[ID($logic_and)] = "ABSY";
|
|
cell_types[ID($logic_or)] = "ABSY";
|
|
|
|
if (edges) {
|
|
cell_types[ID($mux)] = "*";
|
|
cell_types[ID($pmux)] = "*";
|
|
}
|
|
|
|
// cell_types[ID($slice)] = "A";
|
|
// cell_types[ID($concat)] = "A";
|
|
|
|
cell_types[ID($lut)] = "*";
|
|
cell_types[ID($sop)] = "*";
|
|
cell_types[ID($alu)] = "ABSY";
|
|
cell_types[ID($lcu)] = "*";
|
|
cell_types[ID($macc)] = "*";
|
|
cell_types[ID($fa)] = "*";
|
|
|
|
for (; argidx < GetSize(args); argidx++)
|
|
{
|
|
if (args[argidx].rfind("-", 0) == 0)
|
|
log_cmd_error("Unexpected option: %s\n", args[argidx].c_str());
|
|
|
|
if (args[argidx] == "all") {
|
|
for (auto &it : cell_types)
|
|
if (std::count(selected_cell_types.begin(), selected_cell_types.end(), it.first) == 0)
|
|
selected_cell_types.push_back(it.first);
|
|
continue;
|
|
}
|
|
|
|
if (args[argidx].compare(0, 1, "/") == 0) {
|
|
std::vector<IdString> new_selected_cell_types;
|
|
for (auto it : selected_cell_types)
|
|
if (it != args[argidx].substr(1))
|
|
new_selected_cell_types.push_back(it);
|
|
new_selected_cell_types.swap(selected_cell_types);
|
|
continue;
|
|
}
|
|
|
|
if (cell_types.count(args[argidx]) == 0) {
|
|
std::string cell_type_list;
|
|
int charcount = 100;
|
|
for (auto &it : cell_types) {
|
|
if (charcount > 60) {
|
|
cell_type_list += stringf("\n%s", + log_id(it.first));
|
|
charcount = 0;
|
|
} else
|
|
cell_type_list += stringf(" %s", log_id(it.first));
|
|
charcount += GetSize(it.first);
|
|
}
|
|
log_cmd_error("The cell type `%s' is currently not supported. Try one of these:%s\n",
|
|
args[argidx].c_str(), cell_type_list.c_str());
|
|
}
|
|
|
|
if (std::count(selected_cell_types.begin(), selected_cell_types.end(), args[argidx]) == 0)
|
|
selected_cell_types.push_back(args[argidx]);
|
|
}
|
|
|
|
if (!ilang_file.empty()) {
|
|
if (!selected_cell_types.empty())
|
|
log_cmd_error("Do not specify any cell types when using -f.\n");
|
|
selected_cell_types.push_back("ilang");
|
|
}
|
|
|
|
if (selected_cell_types.empty())
|
|
log_cmd_error("No cell type to test specified.\n");
|
|
|
|
std::vector<std::string> uut_names;
|
|
|
|
for (auto cell_type : selected_cell_types)
|
|
for (int i = 0; i < num_iter; i++)
|
|
{
|
|
RTLIL::Design *design = new RTLIL::Design;
|
|
if (cell_type == "ilang")
|
|
Frontend::frontend_call(design, NULL, std::string(), "ilang " + ilang_file);
|
|
else
|
|
create_gold_module(design, cell_type, cell_types.at(cell_type), constmode, muxdiv);
|
|
if (!write_prefix.empty()) {
|
|
Pass::call(design, stringf("write_ilang %s_%s_%05d.il", write_prefix.c_str(), cell_type.c_str()+1, i));
|
|
} else if (edges) {
|
|
Pass::call(design, "dump gold");
|
|
run_edges_test(design, verbose);
|
|
} else {
|
|
Pass::call(design, stringf("copy gold gate; cd gate; %s; cd ..; opt -fast gate", techmap_cmd.c_str()));
|
|
if (!nosat)
|
|
Pass::call(design, "miter -equiv -flatten -make_outputs -ignore_gold_x gold gate miter");
|
|
if (verbose)
|
|
Pass::call(design, "dump gate");
|
|
Pass::call(design, "dump gold");
|
|
if (!nosat)
|
|
Pass::call(design, "sat -verify -enable_undef -prove trigger 0 -show-inputs -show-outputs miter");
|
|
std::string uut_name = stringf("uut_%s_%d", cell_type.substr(1).c_str(), i);
|
|
if (vlog_file.is_open()) {
|
|
Pass::call(design, stringf("copy gold %s_expr; select %s_expr", uut_name.c_str(), uut_name.c_str()));
|
|
Backend::backend_call(design, &vlog_file, "<test_cell -vlog>", "verilog -selected");
|
|
Pass::call(design, stringf("copy gold %s_noexpr; select %s_noexpr", uut_name.c_str(), uut_name.c_str()));
|
|
Backend::backend_call(design, &vlog_file, "<test_cell -vlog>", "verilog -selected -noexpr");
|
|
uut_names.push_back(uut_name);
|
|
}
|
|
if (!noeval)
|
|
run_eval_test(design, verbose, nosat, uut_name, vlog_file);
|
|
}
|
|
delete design;
|
|
}
|
|
|
|
if (vlog_file.is_open()) {
|
|
vlog_file << "\nmodule testbench;\n";
|
|
for (auto &uut : uut_names)
|
|
vlog_file << stringf(" %s %s ();\n", uut.c_str(), uut.c_str());
|
|
vlog_file << " initial begin\n";
|
|
for (auto &uut : uut_names)
|
|
vlog_file << " " << uut << ".run;\n";
|
|
vlog_file << " end\n";
|
|
vlog_file << "endmodule\n";
|
|
}
|
|
}
|
|
} TestCellPass;
|
|
|
|
PRIVATE_NAMESPACE_END
|