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yosys/passes/hierarchy
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Zachary Snow 0d8e5d965f Sign extend port connections where necessary 
- Signed cell outputs are sign extended when bound to larger wires
- Signed connections are sign extended when bound to larger cell inputs
- Sign extension is performed in hierarchy and flatten phases
- genrtlil indirects signed constants through signed wires
- Other phases producing RTLIL may need to be updated to preserve
  signedness information
- Resolves #1418
- Resolves #2265
 		2020-12-18 20:33:14 -07:00
..
Makefile.inc Rename "singleton" pass to "uniquify" 2017-08-20 12:31:50 +02:00
hierarchy.cc Sign extend port connections where necessary 2020-12-18 20:33:14 -07:00
submod.cc Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
uniquify.cc Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00