mirror of https://github.com/YosysHQ/yosys.git
650 lines
17 KiB
C++
650 lines
17 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "blifparse.h"
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YOSYS_NAMESPACE_BEGIN
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static bool read_next_line(char *&buffer, size_t &buffer_size, int &line_count, std::istream &f)
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{
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string strbuf;
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int buffer_len = 0;
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buffer[0] = 0;
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while (1)
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{
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buffer_len += strlen(buffer + buffer_len);
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while (buffer_len > 0 && (buffer[buffer_len-1] == ' ' || buffer[buffer_len-1] == '\t' ||
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buffer[buffer_len-1] == '\r' || buffer[buffer_len-1] == '\n'))
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buffer[--buffer_len] = 0;
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if (buffer_size-buffer_len < 4096) {
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buffer_size *= 2;
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buffer = (char*)realloc(buffer, buffer_size);
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}
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if (buffer_len == 0 || buffer[buffer_len-1] == '\\') {
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if (buffer_len > 0 && buffer[buffer_len-1] == '\\')
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buffer[--buffer_len] = 0;
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line_count++;
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if (!std::getline(f, strbuf))
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return false;
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while (buffer_size-buffer_len < strbuf.size()+1) {
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buffer_size *= 2;
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buffer = (char*)realloc(buffer, buffer_size);
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}
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strcpy(buffer+buffer_len, strbuf.c_str());
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} else
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return true;
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}
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}
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static std::pair<RTLIL::IdString, int> wideports_split(std::string name)
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{
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int pos = -1;
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if (name.empty() || name.back() != ']')
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goto failed;
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for (int i = 0; i+1 < GetSize(name); i++) {
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if (name[i] == '[')
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pos = i;
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else if (name[i] != '-' && (name[i] < '0' || name[i] > '9'))
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pos = -1;
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else if (name[i] == '-' && ((i != pos+1) || name[i+1] == ']'))
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pos = -1;
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else if (i == pos+2 && name[i] == '0' && name[i-1] == '-')
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pos = -1;
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else if (i == pos+1 && name[i] == '0' && name[i+1] != ']')
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pos = -1;
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}
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if (pos >= 0)
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return std::pair<RTLIL::IdString, int>("\\" + name.substr(0, pos), atoi(name.c_str() + pos+1));
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failed:
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return std::pair<RTLIL::IdString, int>(RTLIL::IdString(), 0);
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}
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void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool run_clean, bool sop_mode, bool wideports)
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{
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RTLIL::Module *module = nullptr;
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RTLIL::Const *lutptr = NULL;
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RTLIL::Cell *sopcell = NULL;
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RTLIL::Cell *lastcell = nullptr;
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RTLIL::State lut_default_state = RTLIL::State::Sx;
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std::string err_reason;
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int blif_maxnum = 0, sopmode = -1;
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auto blif_wire = [&](const std::string &wire_name) -> Wire*
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{
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if (wire_name[0] == '$')
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{
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for (int i = 0; i+1 < GetSize(wire_name); i++)
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{
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if (wire_name[i] != '$')
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continue;
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int len = 0;
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while (i+len+1 < GetSize(wire_name) && '0' <= wire_name[i+len+1] && wire_name[i+len+1] <= '9')
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len++;
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if (len > 0) {
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string num_str = wire_name.substr(i+1, len);
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int num = atoi(num_str.c_str()) & 0x0fffffff;
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blif_maxnum = std::max(blif_maxnum, num);
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}
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}
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}
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IdString wire_id = RTLIL::escape_id(wire_name);
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Wire *wire = module->wire(wire_id);
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if (wire == nullptr)
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wire = module->addWire(wire_id);
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return wire;
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};
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dict<RTLIL::IdString, RTLIL::Const> *obj_attributes = nullptr;
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dict<RTLIL::IdString, RTLIL::Const> *obj_parameters = nullptr;
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dict<RTLIL::IdString, std::pair<int, bool>> wideports_cache;
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size_t buffer_size = 4096;
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char *buffer = (char*)malloc(buffer_size);
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int line_count = 0;
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while (1)
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{
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if (!read_next_line(buffer, buffer_size, line_count, f)) {
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if (module != nullptr)
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goto error;
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free(buffer);
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return;
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}
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continue_without_read:
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if (buffer[0] == '#')
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continue;
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if (buffer[0] == '.')
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{
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if (lutptr) {
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for (auto &bit : lutptr->bits)
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if (bit == RTLIL::State::Sx)
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bit = lut_default_state;
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lutptr = NULL;
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lut_default_state = RTLIL::State::Sx;
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}
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if (sopcell) {
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sopcell = NULL;
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sopmode = -1;
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}
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char *cmd = strtok(buffer, " \t\r\n");
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if (!strcmp(cmd, ".model")) {
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if (module != nullptr)
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goto error;
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module = new RTLIL::Module;
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lastcell = nullptr;
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module->name = RTLIL::escape_id(strtok(NULL, " \t\r\n"));
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obj_attributes = &module->attributes;
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obj_parameters = nullptr;
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if (design->module(module->name))
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log_error("Duplicate definition of module %s in line %d!\n", log_id(module->name), line_count);
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design->add(module);
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continue;
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}
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if (module == nullptr)
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goto error;
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if (!strcmp(cmd, ".blackbox"))
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{
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module->attributes[ID::blackbox] = RTLIL::Const(1);
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continue;
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}
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if (!strcmp(cmd, ".end"))
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{
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for (auto &wp : wideports_cache)
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{
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auto name = wp.first;
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int width = wp.second.first;
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bool isinput = wp.second.second;
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RTLIL::Wire *wire = module->addWire(name, width);
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wire->port_input = isinput;
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wire->port_output = !isinput;
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for (int i = 0; i < width; i++) {
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RTLIL::IdString other_name = name.str() + stringf("[%d]", i);
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RTLIL::Wire *other_wire = module->wire(other_name);
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if (other_wire) {
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other_wire->port_input = false;
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other_wire->port_output = false;
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if (isinput)
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module->connect(other_wire, SigSpec(wire, i));
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else
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module->connect(SigSpec(wire, i), other_wire);
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}
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}
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}
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module->fixup_ports();
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wideports_cache.clear();
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if (run_clean)
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{
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Const buffer_lut(vector<RTLIL::State>({State::S0, State::S1}));
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vector<Cell*> remove_cells;
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for (auto cell : module->cells())
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if (cell->type == ID($lut) && cell->getParam(ID::LUT) == buffer_lut) {
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module->connect(cell->getPort(ID::Y), cell->getPort(ID::A));
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remove_cells.push_back(cell);
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}
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for (auto cell : remove_cells)
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module->remove(cell);
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Wire *true_wire = module->wire(ID($true));
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Wire *false_wire = module->wire(ID($false));
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Wire *undef_wire = module->wire(ID($undef));
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if (true_wire != nullptr)
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module->rename(true_wire, stringf("$true$%d", ++blif_maxnum));
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if (false_wire != nullptr)
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module->rename(false_wire, stringf("$false$%d", ++blif_maxnum));
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if (undef_wire != nullptr)
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module->rename(undef_wire, stringf("$undef$%d", ++blif_maxnum));
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autoidx = std::max(autoidx, blif_maxnum+1);
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blif_maxnum = 0;
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}
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module = nullptr;
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lastcell = nullptr;
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obj_attributes = nullptr;
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obj_parameters = nullptr;
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continue;
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}
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if (!strcmp(cmd, ".inputs") || !strcmp(cmd, ".outputs"))
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{
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char *p;
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while ((p = strtok(NULL, " \t\r\n")) != NULL)
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{
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RTLIL::IdString wire_name(stringf("\\%s", p));
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RTLIL::Wire *wire = module->wire(wire_name);
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if (wire == nullptr)
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wire = module->addWire(wire_name);
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if (!strcmp(cmd, ".inputs"))
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wire->port_input = true;
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else
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wire->port_output = true;
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if (wideports) {
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std::pair<RTLIL::IdString, int> wp = wideports_split(p);
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if (!wp.first.empty() && wp.second >= 0) {
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wideports_cache[wp.first].first = std::max(wideports_cache[wp.first].first, wp.second + 1);
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wideports_cache[wp.first].second = !strcmp(cmd, ".inputs");
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}
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}
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}
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obj_attributes = nullptr;
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obj_parameters = nullptr;
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continue;
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}
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if (!strcmp(cmd, ".cname"))
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{
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char *p = strtok(NULL, " \t\r\n");
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if (p == NULL)
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goto error;
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if(lastcell == nullptr || module == nullptr)
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{
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err_reason = stringf("No primitive object to attach .cname %s.", p);
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goto error_with_reason;
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}
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module->rename(lastcell, RTLIL::escape_id(p));
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continue;
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}
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if (!strcmp(cmd, ".attr") || !strcmp(cmd, ".param")) {
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char *n = strtok(NULL, " \t\r\n");
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char *v = strtok(NULL, "\r\n");
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IdString id_n = RTLIL::escape_id(n);
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Const const_v;
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if (v[0] == '"') {
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std::string str(v+1);
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if (str.back() == '"')
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str.resize(str.size()-1);
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const_v = Const(str);
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} else {
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int n = strlen(v);
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const_v.bits.resize(n);
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for (int i = 0; i < n; i++)
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const_v.bits[i] = v[n-i-1] != '0' ? State::S1 : State::S0;
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}
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if (!strcmp(cmd, ".attr")) {
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if (obj_attributes == nullptr) {
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err_reason = stringf("No object to attach .attr too.");
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goto error_with_reason;
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}
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(*obj_attributes)[id_n] = const_v;
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} else {
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if (obj_parameters == nullptr) {
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err_reason = stringf("No object to attach .param too.");
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goto error_with_reason;
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}
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(*obj_parameters)[id_n] = const_v;
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}
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continue;
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}
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if (!strcmp(cmd, ".latch"))
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{
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char *d = strtok(NULL, " \t\r\n");
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char *q = strtok(NULL, " \t\r\n");
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char *edge = strtok(NULL, " \t\r\n");
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char *clock = strtok(NULL, " \t\r\n");
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char *init = strtok(NULL, " \t\r\n");
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RTLIL::Cell *cell = nullptr;
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if (clock == nullptr && edge != nullptr) {
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init = edge;
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edge = nullptr;
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}
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if (init != nullptr && (init[0] == '0' || init[0] == '1'))
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blif_wire(q)->attributes[ID::init] = Const(init[0] == '1' ? 1 : 0, 1);
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if (clock == nullptr)
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goto no_latch_clock;
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if (!strcmp(edge, "re"))
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cell = module->addDff(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q));
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else if (!strcmp(edge, "fe"))
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cell = module->addDff(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false);
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else if (!strcmp(edge, "ah"))
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cell = module->addDlatch(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q));
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else if (!strcmp(edge, "al"))
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cell = module->addDlatch(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false);
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else {
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no_latch_clock:
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if (dff_name.empty()) {
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cell = module->addFf(NEW_ID, blif_wire(d), blif_wire(q));
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} else {
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cell = module->addCell(NEW_ID, dff_name);
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cell->setPort(ID::D, blif_wire(d));
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cell->setPort(ID::Q, blif_wire(q));
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}
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}
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lastcell = cell;
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obj_attributes = &cell->attributes;
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obj_parameters = &cell->parameters;
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continue;
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}
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if (!strcmp(cmd, ".gate") || !strcmp(cmd, ".subckt"))
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{
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char *p = strtok(NULL, " \t\r\n");
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if (p == NULL)
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goto error;
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IdString celltype = RTLIL::escape_id(p);
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RTLIL::Cell *cell = module->addCell(NEW_ID, celltype);
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RTLIL::Module *cell_mod = design->module(celltype);
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dict<RTLIL::IdString, dict<int, SigBit>> cell_wideports_cache;
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while ((p = strtok(NULL, " \t\r\n")) != NULL)
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{
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char *q = strchr(p, '=');
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if (q == NULL || !q[0])
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goto error;
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*(q++) = 0;
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if (wideports) {
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std::pair<RTLIL::IdString, int> wp = wideports_split(p);
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if (wp.first.empty())
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cell->setPort(RTLIL::escape_id(p), *q ? blif_wire(q) : SigSpec());
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else
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cell_wideports_cache[wp.first][wp.second] = blif_wire(q);
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} else {
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cell->setPort(RTLIL::escape_id(p), *q ? blif_wire(q) : SigSpec());
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}
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}
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for (auto &it : cell_wideports_cache)
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{
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int width = 0;
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int offset = 0;
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bool upto = false;
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for (auto &b : it.second)
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width = std::max(width, b.first + 1);
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if (cell_mod) {
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Wire *cell_port = cell_mod->wire(it.first);
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if (cell_port && (cell_port->port_input || cell_port->port_output)) {
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offset = cell_port->start_offset;
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upto = cell_port->upto;
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width = cell_port->width;
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}
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}
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SigSpec sig;
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for (int i = 0; i < width; i++) {
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int idx = offset + (upto ? width - 1 - i: i);
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if (it.second.count(idx))
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sig.append(it.second.at(idx));
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else
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sig.append(module->addWire(NEW_ID));
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}
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cell->setPort(it.first, sig);
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}
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lastcell = cell;
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obj_attributes = &cell->attributes;
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obj_parameters = &cell->parameters;
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continue;
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}
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obj_attributes = nullptr;
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obj_parameters = nullptr;
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if (!strcmp(cmd, ".barbuf") || !strcmp(cmd, ".conn"))
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{
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char *p = strtok(NULL, " \t\r\n");
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if (p == NULL)
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goto error;
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char *q = strtok(NULL, " \t\r\n");
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if (q == NULL)
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goto error;
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module->connect(blif_wire(q), blif_wire(p));
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continue;
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}
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if (!strcmp(cmd, ".names"))
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{
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char *p;
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RTLIL::SigSpec input_sig, output_sig;
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while ((p = strtok(NULL, " \t\r\n")) != NULL)
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input_sig.append(blif_wire(p));
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output_sig = input_sig.extract(input_sig.size()-1, 1);
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input_sig = input_sig.extract(0, input_sig.size()-1);
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if (input_sig.size() == 0)
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{
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RTLIL::State state = RTLIL::State::Sa;
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while (1) {
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if (!read_next_line(buffer, buffer_size, line_count, f))
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goto error;
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for (int i = 0; buffer[i]; i++) {
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if (buffer[i] == ' ' || buffer[i] == '\t')
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continue;
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if (i == 0 && buffer[i] == '.')
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goto finished_parsing_constval;
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if (buffer[i] == '0') {
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if (state == RTLIL::State::S1)
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goto error;
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state = RTLIL::State::S0;
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continue;
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}
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if (buffer[i] == '1') {
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if (state == RTLIL::State::S0)
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goto error;
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state = RTLIL::State::S1;
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continue;
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}
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goto error;
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}
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}
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finished_parsing_constval:
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if (state == RTLIL::State::Sa)
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state = RTLIL::State::S0;
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if (output_sig.as_wire()->name == ID($undef))
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state = RTLIL::State::Sx;
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module->connect(RTLIL::SigSig(output_sig, state));
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goto continue_without_read;
|
|
}
|
|
|
|
if (sop_mode)
|
|
{
|
|
sopcell = module->addCell(NEW_ID, ID($sop));
|
|
sopcell->parameters[ID::WIDTH] = RTLIL::Const(input_sig.size());
|
|
sopcell->parameters[ID::DEPTH] = 0;
|
|
sopcell->parameters[ID::TABLE] = RTLIL::Const();
|
|
sopcell->setPort(ID::A, input_sig);
|
|
sopcell->setPort(ID::Y, output_sig);
|
|
sopmode = -1;
|
|
lastcell = sopcell;
|
|
}
|
|
else
|
|
{
|
|
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($lut));
|
|
cell->parameters[ID::WIDTH] = RTLIL::Const(input_sig.size());
|
|
cell->parameters[ID::LUT] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size());
|
|
cell->setPort(ID::A, input_sig);
|
|
cell->setPort(ID::Y, output_sig);
|
|
lutptr = &cell->parameters.at(ID::LUT);
|
|
lut_default_state = RTLIL::State::Sx;
|
|
lastcell = cell;
|
|
}
|
|
continue;
|
|
}
|
|
|
|
goto error;
|
|
}
|
|
|
|
if (lutptr == NULL && sopcell == NULL)
|
|
goto error;
|
|
|
|
char *input = strtok(buffer, " \t\r\n");
|
|
char *output = strtok(NULL, " \t\r\n");
|
|
|
|
if (input == NULL || output == NULL || (strcmp(output, "0") && strcmp(output, "1")))
|
|
goto error;
|
|
|
|
int input_len = strlen(input);
|
|
|
|
if (sopcell)
|
|
{
|
|
log_assert(sopcell->parameters[ID::WIDTH].as_int() == input_len);
|
|
sopcell->parameters[ID::DEPTH] = sopcell->parameters[ID::DEPTH].as_int() + 1;
|
|
|
|
for (int i = 0; i < input_len; i++)
|
|
switch (input[i]) {
|
|
case '0':
|
|
sopcell->parameters[ID::TABLE].bits.push_back(State::S1);
|
|
sopcell->parameters[ID::TABLE].bits.push_back(State::S0);
|
|
break;
|
|
case '1':
|
|
sopcell->parameters[ID::TABLE].bits.push_back(State::S0);
|
|
sopcell->parameters[ID::TABLE].bits.push_back(State::S1);
|
|
break;
|
|
default:
|
|
sopcell->parameters[ID::TABLE].bits.push_back(State::S0);
|
|
sopcell->parameters[ID::TABLE].bits.push_back(State::S0);
|
|
break;
|
|
}
|
|
|
|
if (sopmode == -1) {
|
|
sopmode = (*output == '1');
|
|
if (!sopmode) {
|
|
SigSpec outnet = sopcell->getPort(ID::Y);
|
|
SigSpec tempnet = module->addWire(NEW_ID);
|
|
module->addNotGate(NEW_ID, tempnet, outnet);
|
|
sopcell->setPort(ID::Y, tempnet);
|
|
}
|
|
} else
|
|
log_assert(sopmode == (*output == '1'));
|
|
}
|
|
|
|
if (lutptr)
|
|
{
|
|
if (input_len > 12)
|
|
goto error;
|
|
|
|
for (int i = 0; i < (1 << input_len); i++) {
|
|
for (int j = 0; j < input_len; j++) {
|
|
char c1 = input[j];
|
|
if (c1 != '-') {
|
|
char c2 = (i & (1 << j)) != 0 ? '1' : '0';
|
|
if (c1 != c2)
|
|
goto try_next_value;
|
|
}
|
|
}
|
|
lutptr->bits.at(i) = !strcmp(output, "0") ? RTLIL::State::S0 : RTLIL::State::S1;
|
|
try_next_value:;
|
|
}
|
|
|
|
lut_default_state = !strcmp(output, "0") ? RTLIL::State::S1 : RTLIL::State::S0;
|
|
}
|
|
}
|
|
|
|
return;
|
|
|
|
error:
|
|
log_error("Syntax error in line %d!\n", line_count);
|
|
error_with_reason:
|
|
log_error("Syntax error in line %d: %s\n", line_count, err_reason.c_str());
|
|
}
|
|
|
|
struct BlifFrontend : public Frontend {
|
|
BlifFrontend() : Frontend("blif", "read BLIF file") { }
|
|
void help() override
|
|
{
|
|
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
|
log("\n");
|
|
log(" read_blif [options] [filename]\n");
|
|
log("\n");
|
|
log("Load modules from a BLIF file into the current design.\n");
|
|
log("\n");
|
|
log(" -sop\n");
|
|
log(" Create $sop cells instead of $lut cells\n");
|
|
log("\n");
|
|
log(" -wideports\n");
|
|
log(" Merge ports that match the pattern 'name[int]' into a single\n");
|
|
log(" multi-bit port 'name'.\n");
|
|
log("\n");
|
|
}
|
|
void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
|
|
{
|
|
bool sop_mode = false;
|
|
bool wideports = false;
|
|
|
|
log_header(design, "Executing BLIF frontend.\n");
|
|
|
|
size_t argidx;
|
|
for (argidx = 1; argidx < args.size(); argidx++) {
|
|
std::string arg = args[argidx];
|
|
if (arg == "-sop") {
|
|
sop_mode = true;
|
|
continue;
|
|
}
|
|
if (arg == "-wideports") {
|
|
wideports = true;
|
|
continue;
|
|
}
|
|
break;
|
|
}
|
|
extra_args(f, filename, args, argidx);
|
|
|
|
parse_blif(design, *f, "", true, sop_mode, wideports);
|
|
}
|
|
} BlifFrontend;
|
|
|
|
YOSYS_NAMESPACE_END
|
|
|