mirror of https://github.com/YosysHQ/yosys.git
16 lines
519 B
Verilog
16 lines
519 B
Verilog
`default_nettype none
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module top ( output wire [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7,
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input wire [15:0] SW );
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sevenseg UUD0 (.HEX0(HEX0), .SW(4'h7));
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sevenseg UUD1 (.HEX0(HEX1), .SW(4'h1));
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sevenseg UUD2 (.HEX0(HEX2), .SW(4'h0));
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sevenseg UUD3 (.HEX0(HEX3), .SW(4'h2));
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sevenseg UUD4 (.HEX0(HEX4), .SW(SW[3:0]));
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sevenseg UUD5 (.HEX0(HEX5), .SW(SW[7:4]));
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sevenseg UUD6 (.HEX0(HEX6), .SW(SW[11:8]));
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sevenseg UUD7 (.HEX0(HEX7), .SW(SW[15:12]));
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endmodule
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