mirror of https://github.com/YosysHQ/yosys.git
123 lines
2.2 KiB
Verilog
123 lines
2.2 KiB
Verilog
module priority_memory (
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clk, wren_a, rden_a, addr_a, wdata_a, rdata_a,
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wren_b, rden_b, addr_b, wdata_b, rdata_b
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);
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parameter ABITS = 12;
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parameter WIDTH = 72;
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input clk;
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input wren_a, rden_a, wren_b, rden_b;
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input [ABITS-1:0] addr_a, addr_b;
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input [WIDTH-1:0] wdata_a, wdata_b;
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output reg [WIDTH-1:0] rdata_a, rdata_b;
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`ifdef USE_HUGE
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(* ram_style = "huge" *)
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`endif
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reg [WIDTH-1:0] mem [0:2**ABITS-1];
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integer i;
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initial begin
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rdata_a <= 'h0;
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rdata_b <= 'h0;
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end
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`ifndef FLIP_PORTS
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always @(posedge clk) begin
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// A port
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if (wren_a)
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mem[addr_a] <= wdata_a;
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else if (rden_a)
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rdata_a <= mem[addr_a];
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// B port
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if (wren_b)
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mem[addr_b] <= wdata_b;
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else if (rden_b)
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if (wren_a && addr_a == addr_b)
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rdata_b <= wdata_a;
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else
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rdata_b <= mem[addr_b];
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end
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`else // FLIP PORTS
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always @(posedge clk) begin
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// A port
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if (wren_b)
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mem[addr_b] <= wdata_b;
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else if (rden_b)
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rdata_b <= mem[addr_b];
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// B port
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if (wren_a)
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mem[addr_a] <= wdata_a;
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else if (rden_a)
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if (wren_b && addr_a == addr_b)
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rdata_a <= wdata_b;
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else
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rdata_a <= mem[addr_a];
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end
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`endif
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endmodule
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module sp_write_first (clk, wren_a, rden_a, addr_a, wdata_a, rdata_a);
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parameter ABITS = 12;
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parameter WIDTH = 72;
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input clk;
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input wren_a, rden_a;
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input [ABITS-1:0] addr_a;
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input [WIDTH-1:0] wdata_a;
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output reg [WIDTH-1:0] rdata_a;
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(* ram_style = "huge" *)
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reg [WIDTH-1:0] mem [0:2**ABITS-1];
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integer i;
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initial begin
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rdata_a <= 'h0;
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end
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always @(posedge clk) begin
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// A port
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if (wren_a)
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mem[addr_a] <= wdata_a;
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if (rden_a)
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if (wren_a)
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rdata_a <= wdata_a;
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else
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rdata_a <= mem[addr_a];
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end
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endmodule
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module sp_read_first (clk, wren_a, rden_a, addr_a, wdata_a, rdata_a);
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parameter ABITS = 12;
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parameter WIDTH = 72;
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input clk;
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input wren_a, rden_a;
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input [ABITS-1:0] addr_a;
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input [WIDTH-1:0] wdata_a;
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output reg [WIDTH-1:0] rdata_a;
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(* ram_style = "huge" *)
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reg [WIDTH-1:0] mem [0:2**ABITS-1];
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integer i;
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initial begin
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rdata_a <= 'h0;
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end
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always @(posedge clk) begin
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// A port
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if (wren_a)
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mem[addr_a] <= wdata_a;
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if (rden_a)
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rdata_a <= mem[addr_a];
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end
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endmodule
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