mirror of https://github.com/YosysHQ/yosys.git
361 lines
11 KiB
C++
361 lines
11 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2014 Clifford Wolf <clifford@clifford.at>
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* Copyright (C) 2014 Johann Glaser <Johann.Glaser@gmx.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/consteval.h"
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#include <algorithm>
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static uint32_t xorshift32_state = 123456789;
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static uint32_t xorshift32(uint32_t limit) {
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xorshift32_state ^= xorshift32_state << 13;
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xorshift32_state ^= xorshift32_state >> 17;
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xorshift32_state ^= xorshift32_state << 5;
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return xorshift32_state % limit;
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}
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static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, std::string cell_type_flags)
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{
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RTLIL::Module *module = design->addModule("\\gold");
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RTLIL::Cell *cell = module->addCell("\\UUT", cell_type);
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RTLIL::Wire *wire;
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if (cell_type == "$lut")
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{
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int width = 1 + xorshift32(6);
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wire = module->addWire("\\A");
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wire->width = width;
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wire->port_input = true;
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cell->setPort("\\A", wire);
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wire = module->addWire("\\Y");
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wire->port_output = true;
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cell->setPort("\\Y", wire);
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RTLIL::SigSpec config;
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for (int i = 0; i < (1 << width); i++)
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config.append(xorshift32(2) ? RTLIL::S1 : RTLIL::S0);
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cell->setParam("\\LUT", config.as_const());
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}
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if (cell_type_flags.find('A') != std::string::npos) {
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wire = module->addWire("\\A");
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wire->width = 1 + xorshift32(8);
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wire->port_input = true;
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cell->setPort("\\A", wire);
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}
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if (cell_type_flags.find('B') != std::string::npos) {
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wire = module->addWire("\\B");
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if (cell_type_flags.find('h') != std::string::npos)
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wire->width = 1 + xorshift32(6);
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else
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wire->width = 1 + xorshift32(8);
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wire->port_input = true;
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cell->setPort("\\B", wire);
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}
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if (cell_type_flags.find('S') != std::string::npos && xorshift32(2)) {
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if (cell_type_flags.find('A') != std::string::npos)
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cell->parameters["\\A_SIGNED"] = true;
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if (cell_type_flags.find('B') != std::string::npos)
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cell->parameters["\\B_SIGNED"] = true;
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}
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if (cell_type_flags.find('s') != std::string::npos) {
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if (cell_type_flags.find('A') != std::string::npos && xorshift32(2))
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cell->parameters["\\A_SIGNED"] = true;
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if (cell_type_flags.find('B') != std::string::npos && xorshift32(2))
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cell->parameters["\\B_SIGNED"] = true;
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}
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if (cell_type_flags.find('Y') != std::string::npos) {
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wire = module->addWire("\\Y");
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wire->width = 1 + xorshift32(8);
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wire->port_output = true;
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cell->setPort("\\Y", wire);
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}
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module->fixup_ports();
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cell->fixup_parameters();
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cell->check();
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}
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static void run_eval_test(RTLIL::Design *design)
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{
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RTLIL::Module *gold_mod = design->module("\\gold");
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RTLIL::Module *gate_mod = design->module("\\gate");
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ConstEval gold_ce(gold_mod), gate_ce(gate_mod);
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log("Eval testing: ");
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for (int i = 0; i < 64; i++)
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{
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log(".");
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gold_ce.clear();
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gate_ce.clear();
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for (auto port : gold_mod->ports)
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{
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RTLIL::Wire *gold_wire = gold_mod->wire(port);
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RTLIL::Wire *gate_wire = gate_mod->wire(port);
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log_assert(gold_wire != nullptr);
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log_assert(gate_wire != nullptr);
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log_assert(gold_wire->port_input == gate_wire->port_input);
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log_assert(SIZE(gold_wire) == SIZE(gate_wire));
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if (!gold_wire->port_input)
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continue;
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RTLIL::Const in_value;
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for (int i = 0; i < SIZE(gold_wire); i++)
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in_value.bits.push_back(xorshift32(2) ? RTLIL::S1 : RTLIL::S0);
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if (xorshift32(4) == 0) {
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int inv_chance = 1 + xorshift32(8);
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for (int i = 0; i < SIZE(gold_wire); i++)
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if (xorshift32(inv_chance) == 0)
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in_value.bits[i] = RTLIL::Sx;
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}
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// log("%s: %s\n", log_id(gold_wire), log_signal(in_value));
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gold_ce.set(gold_wire, in_value);
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gate_ce.set(gate_wire, in_value);
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}
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for (auto port : gold_mod->ports)
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{
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RTLIL::Wire *gold_wire = gold_mod->wire(port);
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RTLIL::Wire *gate_wire = gate_mod->wire(port);
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log_assert(gold_wire != nullptr);
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log_assert(gate_wire != nullptr);
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log_assert(gold_wire->port_output == gate_wire->port_output);
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log_assert(SIZE(gold_wire) == SIZE(gate_wire));
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if (!gold_wire->port_output)
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continue;
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RTLIL::SigSpec gold_outval(gold_wire);
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RTLIL::SigSpec gate_outval(gate_wire);
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if (!gold_ce.eval(gold_outval))
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log_error("Failed to eval %s in gold module.\n", log_id(gold_wire));
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if (!gate_ce.eval(gate_outval))
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log_error("Failed to eval %s in gate module.\n", log_id(gate_wire));
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bool gold_gate_mismatch = false;
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for (int i = 0; i < SIZE(gold_wire); i++) {
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if (gold_outval[i] == RTLIL::Sx)
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continue;
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if (gold_outval[i] == gate_outval[i])
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continue;
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gold_gate_mismatch = true;
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break;
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}
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if (gold_gate_mismatch)
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log_error("Mismatch in output %s: gold:%s != gate:%s\n", log_id(gate_wire), log_signal(gold_outval), log_signal(gate_outval));
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// log("%s: %s\n", log_id(gold_wire), log_signal(gold_outval));
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}
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}
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log(" ok.\n");
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}
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struct TestCellPass : public Pass {
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TestCellPass() : Pass("test_cell", "automatically test the implementation of a cell type") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" test_cell [options] {cell-types}\n");
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log("\n");
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log("Tests the internal implementation of the given cell type (for example '$mux')\n");
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log("by comparing SAT solver, EVAL and TECHMAP implementations of the cell types..\n");
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log("\n");
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log("Run with 'all' instead of a cell type to run the test on all supported\n");
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log("cell types.\n");
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log("\n");
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log(" -n {integer}\n");
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log(" create this number of cell instances and test them (default = 100).\n");
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log("\n");
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log(" -s {positive_integer}\n");
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log(" use this value as rng seed value (default = unix time).\n");
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log("\n");
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log(" -f {ilang_file}\n");
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log(" don't generate circuits. instead load the specified ilang file.\n");
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log("\n");
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log(" -map {filename}\n");
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log(" pass this option to techmap.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design*)
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{
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int num_iter = 100;
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std::string techmap_cmd = "techmap -assert";
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std::string ilang_file;
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xorshift32_state = 0;
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int argidx;
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for (argidx = 1; argidx < SIZE(args); argidx++)
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{
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if (args[argidx] == "-n" && argidx+1 < SIZE(args)) {
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num_iter = atoi(args[++argidx].c_str());
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continue;
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}
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if (args[argidx] == "-s" && argidx+1 < SIZE(args)) {
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xorshift32_state = atoi(args[++argidx].c_str());
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continue;
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}
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if (args[argidx] == "-map" && argidx+1 < SIZE(args)) {
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techmap_cmd += " -map " + args[++argidx];
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continue;
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}
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if (args[argidx] == "-f" && argidx+1 < SIZE(args)) {
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ilang_file = args[++argidx];
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num_iter = 1;
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continue;
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}
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break;
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}
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if (xorshift32_state == 0)
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xorshift32_state = time(NULL);
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std::map<std::string, std::string> cell_types;
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std::vector<std::string> selected_cell_types;
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cell_types["$not"] = "ASY";
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cell_types["$pos"] = "ASY";
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cell_types["$bu0"] = "ASY";
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cell_types["$neg"] = "ASY";
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cell_types["$and"] = "ABSY";
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cell_types["$or"] = "ABSY";
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cell_types["$xor"] = "ABSY";
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cell_types["$xnor"] = "ABSY";
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cell_types["$reduce_and"] = "ASY";
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cell_types["$reduce_or"] = "ASY";
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cell_types["$reduce_xor"] = "ASY";
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cell_types["$reduce_xnor"] = "ASY";
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cell_types["$reduce_bool"] = "ASY";
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cell_types["$shl"] = "ABshY";
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cell_types["$shr"] = "ABshY";
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cell_types["$sshl"] = "ABshY";
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cell_types["$sshr"] = "ABshY";
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cell_types["$shift"] = "ABshY";
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cell_types["$shiftx"] = "ABshY";
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cell_types["$lt"] = "ABSY";
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cell_types["$le"] = "ABSY";
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cell_types["$eq"] = "ABSY";
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cell_types["$ne"] = "ABSY";
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// cell_types["$eqx"] = "ABSY";
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// cell_types["$nex"] = "ABSY";
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cell_types["$ge"] = "ABSY";
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cell_types["$gt"] = "ABSY";
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cell_types["$add"] = "ABSY";
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cell_types["$sub"] = "ABSY";
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cell_types["$mul"] = "ABSY";
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cell_types["$div"] = "ABSY";
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cell_types["$mod"] = "ABSY";
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// cell_types["$pow"] = "ABsY";
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cell_types["$logic_not"] = "ASY";
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cell_types["$logic_and"] = "ABSY";
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cell_types["$logic_or"] = "ABSY";
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// cell_types["$mux"] = "A";
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// cell_types["$pmux"] = "A";
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// cell_types["$slice"] = "A";
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// cell_types["$concat"] = "A";
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// cell_types["$assert"] = "A";
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cell_types["$lut"] = "*";
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// cell_types["$alu"] = "*";
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for (; argidx < SIZE(args); argidx++)
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{
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if (args[argidx].rfind("-", 0) == 0)
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log_cmd_error("Unexpected option: %s\n", args[argidx].c_str());
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if (args[argidx] == "all") {
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for (auto &it : cell_types)
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if (std::count(selected_cell_types.begin(), selected_cell_types.end(), it.first) == 0)
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selected_cell_types.push_back(it.first);
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continue;
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}
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if (cell_types.count(args[argidx]) == 0) {
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std::string cell_type_list;
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int charcount = 100;
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for (auto &it : cell_types) {
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if (charcount > 60) {
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cell_type_list += "\n" + it.first;
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charcount = 0;
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} else
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cell_type_list += " " + it.first;
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charcount += SIZE(it.first);
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}
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log_cmd_error("The cell type `%s' is currently not supported. Try one of these:%s\n",
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args[argidx].c_str(), cell_type_list.c_str());
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}
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if (std::count(selected_cell_types.begin(), selected_cell_types.end(), args[argidx]) == 0)
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selected_cell_types.push_back(args[argidx]);
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}
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if (!ilang_file.empty()) {
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if (!selected_cell_types.empty())
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log_cmd_error("Do not specify any cell types when using -f.\n");
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selected_cell_types.push_back("ilang");
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}
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if (selected_cell_types.empty())
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log_cmd_error("No cell type to test specified.\n");
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for (auto cell_type : selected_cell_types)
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for (int i = 0; i < num_iter; i++)
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{
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RTLIL::Design *design = new RTLIL::Design;
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if (cell_type == "ilang")
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Frontend::frontend_call(design, NULL, std::string(), "ilang " + ilang_file);
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else
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create_gold_module(design, cell_type, cell_types.at(cell_type));
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Pass::call(design, stringf("copy gold gate; %s gate; opt gate", techmap_cmd.c_str()));
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Pass::call(design, "miter -equiv -flatten -make_outputs -ignore_gold_x gold gate miter; dump gold");
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Pass::call(design, "sat -verify -enable_undef -prove trigger 0 -show-inputs -show-outputs miter");
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run_eval_test(design);
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delete design;
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}
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}
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} TestCellPass;
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