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.gitignore
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Add test for writing gzip-compressed files
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2019-08-06 17:43:04 +01:00 |
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abc9.v
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Add test
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2019-07-02 19:13:40 -07:00 |
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abc9.ys
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Update test with more accurate LUT mask
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2019-07-12 21:00:59 -07:00 |
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async.sh
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Improve tests/various/async, disable failing ffl test
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2019-07-09 22:21:25 +02:00 |
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async.v
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Fix tests/various/async FFL test
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2019-07-09 22:44:39 +02:00 |
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attrib05_port_conn.v
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Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.
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2019-06-04 10:42:42 +02:00 |
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attrib05_port_conn.ys
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Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.
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2019-06-04 10:42:42 +02:00 |
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attrib07_func_call.v
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Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.
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2019-06-04 10:42:42 +02:00 |
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attrib07_func_call.ys
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Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.
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2019-06-04 10:42:42 +02:00 |
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chparam.sh
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Add tests/various/chparam.sh
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2019-05-06 16:03:15 +02:00 |
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constmsk_test.v
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Added tests/various/constmsk_test.ys
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2014-09-04 15:07:30 +02:00 |
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constmsk_test.ys
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Added tests/various/constmsk_test.ys
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2014-09-04 15:07:30 +02:00 |
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constmsk_testmap.v
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Added tests/various/constmsk_test.ys
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2014-09-04 15:07:30 +02:00 |
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elab_sys_tasks.sv
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Initial implementation of elaboration system tasks
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2019-05-03 03:10:43 +03:00 |
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elab_sys_tasks.ys
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Initial implementation of elaboration system tasks
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2019-05-03 03:10:43 +03:00 |
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gzip_verilog.v.gz
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Add support for reading gzip'd input files
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2019-07-26 10:23:58 +01:00 |
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gzip_verilog.ys
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Add support for reading gzip'd input files
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2019-07-26 10:23:58 +01:00 |
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hierarchy.sh
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Fix tests
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2019-04-21 11:40:20 +02:00 |
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muxcover.ys
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Merge origin/master
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2019-06-27 11:20:15 -07:00 |
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muxpack.v
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Add more tests
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2019-06-21 12:31:04 -07:00 |
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muxpack.ys
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Add more tests
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2019-06-21 12:31:04 -07:00 |
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opt_expr.ys
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Merge remote-tracking branch 'origin/master' into eddie/fix_1262
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2019-08-11 21:13:40 -07:00 |
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opt_rmdff.v
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Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"
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2019-08-10 17:14:48 +01:00 |
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opt_rmdff.ys
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Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"
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2019-08-10 17:14:48 +01:00 |
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pmux2shiftx.v
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Add #1135 testcase
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2019-06-27 11:02:52 -07:00 |
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pmux2shiftx.ys
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Add #1135 testcase
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2019-06-27 11:02:52 -07:00 |
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reg_wire_error.sv
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Modified errors into warnings
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2018-06-05 18:03:22 +03:00 |
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reg_wire_error.ys
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reg_wire_error test needs the -sv flag so it is run via a script so it had to be moved out of the tests/simple dir that only runs Verilog files
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2018-06-05 18:00:06 +03:00 |
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run-test.sh
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Improve tests/various/run-test.sh
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2019-07-09 20:58:28 +02:00 |
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script.ys
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Update test for Pass::call_on_module()
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2019-07-02 08:22:31 -07:00 |
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shregmap.v
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Add shregmap -tech xilinx test
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2019-06-12 08:34:06 -07:00 |
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shregmap.ys
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Add shregmap -tech xilinx test
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2019-06-12 08:34:06 -07:00 |
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signext.ys
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Extend sign extension tests
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2019-06-20 12:43:59 -07:00 |
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specify.v
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Fix tests/various/specify.v
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2019-07-03 11:25:05 +02:00 |
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specify.ys
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Fix tests/various/specify.v
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2019-07-03 11:25:05 +02:00 |
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submod_extract.ys
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Added tests/various/submod_extract.ys
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2014-07-26 17:22:18 +02:00 |
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wreduce.ys
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Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"
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2019-08-10 17:14:48 +01:00 |
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write_gzip.ys
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Do not use Verific in tests/various/write_gzip.ys
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2019-08-16 14:22:46 +02:00 |
40c40d9f5d