mirror of https://github.com/YosysHQ/yosys.git
586 lines
15 KiB
C++
586 lines
15 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/macc.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct AlumaccWorker
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{
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RTLIL::Module *module;
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SigMap sigmap;
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struct maccnode_t {
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Macc macc;
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RTLIL::Cell *cell;
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RTLIL::SigSpec y;
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int users;
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};
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struct alunode_t
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{
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std::vector<RTLIL::Cell*> cells;
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RTLIL::SigSpec a, b, c, y;
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std::vector<tuple<bool, bool, bool, bool, RTLIL::SigSpec>> cmp;
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bool is_signed, invert_b;
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RTLIL::Cell *alu_cell;
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RTLIL::SigSpec cached_lt, cached_gt, cached_eq, cached_ne;
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RTLIL::SigSpec cached_cf, cached_of, cached_sf;
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RTLIL::SigSpec get_lt() {
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if (GetSize(cached_lt) == 0) {
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if (is_signed) {
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get_of();
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get_sf();
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cached_lt = alu_cell->module->Xor(NEW_ID, cached_of, cached_sf);
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}
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else
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cached_lt = get_cf();
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}
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return cached_lt;
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}
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RTLIL::SigSpec get_gt() {
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if (GetSize(cached_gt) == 0) {
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get_lt();
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get_eq();
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SigSpec Or = alu_cell->module->Or(NEW_ID, cached_lt, cached_eq);
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cached_gt = alu_cell->module->Not(NEW_ID, Or, false, alu_cell->get_src_attribute());
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}
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return cached_gt;
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}
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RTLIL::SigSpec get_eq() {
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if (GetSize(cached_eq) == 0)
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cached_eq = alu_cell->module->ReduceAnd(NEW_ID, alu_cell->getPort(ID::X), false, alu_cell->get_src_attribute());
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return cached_eq;
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}
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RTLIL::SigSpec get_ne() {
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if (GetSize(cached_ne) == 0)
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cached_ne = alu_cell->module->Not(NEW_ID, get_eq(), false, alu_cell->get_src_attribute());
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return cached_ne;
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}
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RTLIL::SigSpec get_cf() {
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if (GetSize(cached_cf) == 0) {
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cached_cf = alu_cell->getPort(ID::CO);
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log_assert(GetSize(cached_cf) >= 1);
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cached_cf = alu_cell->module->Not(NEW_ID, cached_cf[GetSize(cached_cf)-1], false, alu_cell->get_src_attribute());
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}
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return cached_cf;
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}
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RTLIL::SigSpec get_of() {
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if (GetSize(cached_of) == 0) {
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cached_of = {alu_cell->getPort(ID::CO), alu_cell->getPort(ID::CI)};
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log_assert(GetSize(cached_of) >= 2);
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cached_of = alu_cell->module->Xor(NEW_ID, cached_of[GetSize(cached_of)-1], cached_of[GetSize(cached_of)-2]);
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}
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return cached_of;
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}
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RTLIL::SigSpec get_sf() {
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if (GetSize(cached_sf) == 0) {
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cached_sf = alu_cell->getPort(ID::Y);
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cached_sf = cached_sf[GetSize(cached_sf)-1];
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}
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return cached_sf;
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}
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};
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dict<RTLIL::SigBit, int> bit_users;
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dict<RTLIL::SigSpec, maccnode_t*> sig_macc;
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dict<RTLIL::SigSig, pool<alunode_t*>> sig_alu;
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int macc_counter, alu_counter;
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AlumaccWorker(RTLIL::Module *module) : module(module), sigmap(module)
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{
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macc_counter = 0;
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alu_counter = 0;
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}
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void count_bit_users()
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{
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for (auto port : module->ports)
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for (auto bit : sigmap(module->wire(port)))
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bit_users[bit]++;
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for (auto cell : module->cells())
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for (auto &conn : cell->connections())
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for (auto bit : sigmap(conn.second))
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bit_users[bit]++;
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}
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void extract_macc()
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{
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for (auto cell : module->selected_cells())
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{
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if (!cell->type.in(ID($pos), ID($neg), ID($add), ID($sub), ID($mul)))
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continue;
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log(" creating $macc model for %s (%s).\n", log_id(cell), log_id(cell->type));
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maccnode_t *n = new maccnode_t;
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Macc::port_t new_port;
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n->cell = cell;
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n->y = sigmap(cell->getPort(ID::Y));
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n->users = 0;
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for (auto bit : n->y)
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n->users = max(n->users, bit_users.at(bit) - 1);
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if (cell->type.in(ID($pos), ID($neg)))
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{
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new_port.in_a = sigmap(cell->getPort(ID::A));
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new_port.is_signed = cell->getParam(ID::A_SIGNED).as_bool();
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new_port.do_subtract = cell->type == ID($neg);
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n->macc.ports.push_back(new_port);
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}
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if (cell->type.in(ID($add), ID($sub)))
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{
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new_port.in_a = sigmap(cell->getPort(ID::A));
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new_port.is_signed = cell->getParam(ID::A_SIGNED).as_bool();
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new_port.do_subtract = false;
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n->macc.ports.push_back(new_port);
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new_port.in_a = sigmap(cell->getPort(ID::B));
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new_port.is_signed = cell->getParam(ID::B_SIGNED).as_bool();
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new_port.do_subtract = cell->type == ID($sub);
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n->macc.ports.push_back(new_port);
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}
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if (cell->type.in(ID($mul)))
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{
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new_port.in_a = sigmap(cell->getPort(ID::A));
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new_port.in_b = sigmap(cell->getPort(ID::B));
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new_port.is_signed = cell->getParam(ID::A_SIGNED).as_bool();
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new_port.do_subtract = false;
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n->macc.ports.push_back(new_port);
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}
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log_assert(sig_macc.count(n->y) == 0);
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sig_macc[n->y] = n;
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}
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}
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static bool macc_may_overflow(Macc &macc, int width, bool is_signed)
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{
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std::vector<int> port_sizes;
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for (auto &port : macc.ports) {
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if (port.is_signed != is_signed)
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return true;
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if (!port.is_signed && port.do_subtract)
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return true;
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if (GetSize(port.in_b))
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port_sizes.push_back(GetSize(port.in_a) + GetSize(port.in_b));
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else
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port_sizes.push_back(GetSize(port.in_a));
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}
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std::sort(port_sizes.begin(), port_sizes.end());
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int acc_sum = 0, acc_shift = 0;
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for (int sz : port_sizes) {
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while ((sz - acc_shift) > 20) {
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if (acc_sum & 1)
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acc_sum++;
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acc_sum = acc_sum >> 1;
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acc_shift++;
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}
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acc_sum += (1 << (sz - acc_shift)) - 1;
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}
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while (acc_sum) {
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acc_sum = acc_sum >> 1;
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acc_shift++;
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}
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return acc_shift > width;
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}
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void merge_macc()
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{
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while (1)
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{
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pool<maccnode_t*> delete_nodes;
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for (auto &it : sig_macc)
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{
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auto n = it.second;
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if (delete_nodes.count(n))
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continue;
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for (int i = 0; i < GetSize(n->macc.ports); i++)
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{
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auto &port = n->macc.ports[i];
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if (GetSize(port.in_b) > 0 || sig_macc.count(port.in_a) == 0)
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continue;
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auto other_n = sig_macc.at(port.in_a);
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if (other_n->users > 1)
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continue;
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if (GetSize(other_n->y) != GetSize(n->y) && macc_may_overflow(other_n->macc, GetSize(other_n->y), port.is_signed))
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continue;
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log(" merging $macc model for %s into %s.\n", log_id(other_n->cell), log_id(n->cell));
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bool do_subtract = port.do_subtract;
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for (int j = 0; j < GetSize(other_n->macc.ports); j++) {
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if (do_subtract)
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other_n->macc.ports[j].do_subtract = !other_n->macc.ports[j].do_subtract;
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if (j == 0)
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n->macc.ports[i--] = other_n->macc.ports[j];
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else
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n->macc.ports.push_back(other_n->macc.ports[j]);
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}
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delete_nodes.insert(other_n);
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}
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}
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if (delete_nodes.empty())
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break;
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for (auto n : delete_nodes) {
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sig_macc.erase(n->y);
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delete n;
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}
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}
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}
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void macc_to_alu()
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{
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pool<maccnode_t*> delete_nodes;
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for (auto &it : sig_macc)
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{
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auto n = it.second;
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RTLIL::SigSpec A, B, C = n->macc.bit_ports;
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bool a_signed = false, b_signed = false;
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bool subtract_b = false;
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alunode_t *alunode;
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for (auto &port : n->macc.ports)
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if (GetSize(port.in_b) > 0) {
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goto next_macc;
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} else if (GetSize(port.in_a) == 1 && !port.is_signed && !port.do_subtract) {
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C.append(port.in_a);
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} else if (GetSize(A) || port.do_subtract) {
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if (GetSize(B))
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goto next_macc;
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B = port.in_a;
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b_signed = port.is_signed;
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subtract_b = port.do_subtract;
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} else {
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if (GetSize(A))
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goto next_macc;
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A = port.in_a;
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a_signed = port.is_signed;
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}
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if (!a_signed || !b_signed) {
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if (GetSize(A) == GetSize(n->y))
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a_signed = false;
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if (GetSize(B) == GetSize(n->y))
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b_signed = false;
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if (a_signed != b_signed)
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goto next_macc;
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}
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if (GetSize(A) == 0 && GetSize(C) > 0) {
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A = C[0];
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C.remove(0);
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}
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if (GetSize(B) == 0 && GetSize(C) > 0) {
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B = C[0];
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C.remove(0);
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}
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if (subtract_b)
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C.append(State::S1);
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if (GetSize(C) > 1)
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goto next_macc;
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if (!subtract_b && B < A && GetSize(B))
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std::swap(A, B);
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log(" creating $alu model for $macc %s.\n", log_id(n->cell));
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alunode = new alunode_t;
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alunode->cells.push_back(n->cell);
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alunode->is_signed = a_signed;
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alunode->invert_b = subtract_b;
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alunode->a = A;
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alunode->b = B;
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alunode->c = C;
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alunode->y = n->y;
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sig_alu[RTLIL::SigSig(A, B)].insert(alunode);
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delete_nodes.insert(n);
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next_macc:;
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}
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for (auto n : delete_nodes) {
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sig_macc.erase(n->y);
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delete n;
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}
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}
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void replace_macc()
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{
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for (auto &it : sig_macc)
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{
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auto n = it.second;
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auto cell = module->addCell(NEW_ID, ID($macc));
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macc_counter++;
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log(" creating $macc cell for %s: %s\n", log_id(n->cell), log_id(cell));
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cell->set_src_attribute(n->cell->get_src_attribute());
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n->macc.optimize(GetSize(n->y));
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n->macc.to_cell(cell);
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cell->setPort(ID::Y, n->y);
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cell->fixup_parameters();
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module->remove(n->cell);
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delete n;
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}
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sig_macc.clear();
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}
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void extract_cmp_alu()
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{
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std::vector<RTLIL::Cell*> lge_cells, eq_cells;
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for (auto cell : module->selected_cells())
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{
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if (cell->type.in(ID($lt), ID($le), ID($ge), ID($gt)))
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lge_cells.push_back(cell);
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if (cell->type.in(ID($eq), ID($eqx), ID($ne), ID($nex)))
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eq_cells.push_back(cell);
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}
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for (auto cell : lge_cells)
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{
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log(" creating $alu model for %s (%s):", log_id(cell), log_id(cell->type));
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bool cmp_less = cell->type.in(ID($lt), ID($le));
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bool cmp_equal = cell->type.in(ID($le), ID($ge));
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bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
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RTLIL::SigSpec A = sigmap(cell->getPort(ID::A));
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RTLIL::SigSpec B = sigmap(cell->getPort(ID::B));
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RTLIL::SigSpec Y = sigmap(cell->getPort(ID::Y));
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if (B < A && GetSize(B)) {
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cmp_less = !cmp_less;
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std::swap(A, B);
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}
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alunode_t *n = nullptr;
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for (auto node : sig_alu[RTLIL::SigSig(A, B)])
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if (node->is_signed == is_signed && node->invert_b && node->c == State::S1) {
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n = node;
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break;
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}
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if (n == nullptr) {
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n = new alunode_t;
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n->a = A;
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n->b = B;
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n->c = State::S1;
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n->y = module->addWire(NEW_ID, max(GetSize(A), GetSize(B)));
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n->is_signed = is_signed;
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n->invert_b = true;
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sig_alu[RTLIL::SigSig(A, B)].insert(n);
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log(" new $alu\n");
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} else {
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log(" merged with %s.\n", log_id(n->cells.front()));
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}
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n->cells.push_back(cell);
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n->cmp.push_back(std::make_tuple(cmp_less, !cmp_less, cmp_equal, false, Y));
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}
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for (auto cell : eq_cells)
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{
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bool cmp_equal = cell->type.in(ID($eq), ID($eqx));
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bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
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RTLIL::SigSpec A = sigmap(cell->getPort(ID::A));
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RTLIL::SigSpec B = sigmap(cell->getPort(ID::B));
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RTLIL::SigSpec Y = sigmap(cell->getPort(ID::Y));
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if (B < A && GetSize(B))
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std::swap(A, B);
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alunode_t *n = nullptr;
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for (auto node : sig_alu[RTLIL::SigSig(A, B)])
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if (node->is_signed == is_signed && node->invert_b && node->c == State::S1) {
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n = node;
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break;
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}
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if (n != nullptr) {
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log(" creating $alu model for %s (%s): merged with %s.\n", log_id(cell), log_id(cell->type), log_id(n->cells.front()));
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n->cells.push_back(cell);
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n->cmp.push_back(std::make_tuple(false, false, cmp_equal, !cmp_equal, Y));
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}
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}
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}
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void replace_alu()
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{
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std::string src("");
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for (auto &it1 : sig_alu)
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for (auto n : it1.second)
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{
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if (GetSize(n->b) == 0 && GetSize(n->c) == 0 && GetSize(n->cmp) == 0)
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{
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n->alu_cell = module->addPos(NEW_ID, n->a, n->y, n->is_signed);
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log(" creating $pos cell for ");
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for (int i = 0; i < GetSize(n->cells); i++)
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log("%s%s", i ? ", ": "", log_id(n->cells[i]));
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log(": %s\n", log_id(n->alu_cell));
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goto delete_node;
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}
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n->alu_cell = module->addCell(NEW_ID, ID($alu));
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alu_counter++;
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log(" creating $alu cell for ");
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for (int i = 0; i < GetSize(n->cells); i++)
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log("%s%s", i ? ", ": "", log_id(n->cells[i]));
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log(": %s\n", log_id(n->alu_cell));
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if (n->cells.size() > 0)
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n->alu_cell->set_src_attribute(n->cells[0]->get_src_attribute());
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|
n->alu_cell->setPort(ID::A, n->a);
|
|
n->alu_cell->setPort(ID::B, n->b);
|
|
n->alu_cell->setPort(ID::CI, GetSize(n->c) ? n->c : State::S0);
|
|
n->alu_cell->setPort(ID::BI, n->invert_b ? State::S1 : State::S0);
|
|
n->alu_cell->setPort(ID::Y, n->y);
|
|
n->alu_cell->setPort(ID::X, module->addWire(NEW_ID, GetSize(n->y)));
|
|
n->alu_cell->setPort(ID::CO, module->addWire(NEW_ID, GetSize(n->y)));
|
|
n->alu_cell->fixup_parameters(n->is_signed, n->is_signed);
|
|
|
|
for (auto &it : n->cmp)
|
|
{
|
|
bool cmp_lt = std::get<0>(it);
|
|
bool cmp_gt = std::get<1>(it);
|
|
bool cmp_eq = std::get<2>(it);
|
|
bool cmp_ne = std::get<3>(it);
|
|
RTLIL::SigSpec cmp_y = std::get<4>(it);
|
|
|
|
RTLIL::SigSpec sig;
|
|
if (cmp_lt) sig.append(n->get_lt());
|
|
if (cmp_gt) sig.append(n->get_gt());
|
|
if (cmp_eq) sig.append(n->get_eq());
|
|
if (cmp_ne) sig.append(n->get_ne());
|
|
|
|
if (GetSize(sig) > 1)
|
|
sig = module->ReduceOr(NEW_ID, sig);
|
|
|
|
sig.extend_u0(GetSize(cmp_y));
|
|
module->connect(cmp_y, sig);
|
|
}
|
|
|
|
delete_node:
|
|
for (auto c : n->cells)
|
|
module->remove(c);
|
|
delete n;
|
|
}
|
|
|
|
sig_alu.clear();
|
|
}
|
|
|
|
void run()
|
|
{
|
|
log("Extracting $alu and $macc cells in module %s:\n", log_id(module));
|
|
|
|
count_bit_users();
|
|
extract_macc();
|
|
merge_macc();
|
|
macc_to_alu();
|
|
replace_macc();
|
|
extract_cmp_alu();
|
|
replace_alu();
|
|
|
|
log(" created %d $alu and %d $macc cells.\n", alu_counter, macc_counter);
|
|
}
|
|
};
|
|
|
|
struct AlumaccPass : public Pass {
|
|
AlumaccPass() : Pass("alumacc", "extract ALU and MACC cells") { }
|
|
void help() override
|
|
{
|
|
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
|
log("\n");
|
|
log(" alumacc [selection]\n");
|
|
log("\n");
|
|
log("This pass translates arithmetic operations like $add, $mul, $lt, etc. to $alu\n");
|
|
log("and $macc cells.\n");
|
|
log("\n");
|
|
}
|
|
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
|
{
|
|
log_header(design, "Executing ALUMACC pass (create $alu and $macc cells).\n");
|
|
|
|
size_t argidx;
|
|
for (argidx = 1; argidx < args.size(); argidx++) {
|
|
// if (args[argidx] == "-foobar") {
|
|
// foobar_mode = true;
|
|
// continue;
|
|
// }
|
|
break;
|
|
}
|
|
extra_args(args, argidx, design);
|
|
|
|
for (auto mod : design->selected_modules())
|
|
if (!mod->has_processes_warn()) {
|
|
AlumaccWorker worker(mod);
|
|
worker.run();
|
|
}
|
|
}
|
|
} AlumaccPass;
|
|
|
|
PRIVATE_NAMESPACE_END
|