mirror of https://github.com/YosysHQ/yosys.git
29 lines
869 B
Plaintext
29 lines
869 B
Plaintext
read_verilog ../common/mul.v
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hierarchy -top top
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proc
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design -save read
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equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 7 t:CCU2
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select -assert-max 5 t:WIDEFN9
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select -assert-max 62 t:LUT4
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select -assert-none t:IB t:OB t:VLO t:VHI t:LUT4 t:CCU2 t:WIDEFN9 %% t:* %D
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design -load read
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equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus -abc9
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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stat
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select -assert-count 7 t:CCU2
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select -assert-max 12 t:WIDEFN9
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select -assert-max 58 t:LUT4
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select -assert-none t:IB t:OB t:VLO t:VHI t:LUT4 t:CCU2 t:WIDEFN9 %% t:* %D
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