mirror of https://github.com/YosysHQ/yosys.git
129 lines
3.8 KiB
C++
129 lines
3.8 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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struct DesignPass : public Pass {
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DesignPass() : Pass("design", "save, restore and reset current design") { }
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std::map<std::string, RTLIL::Design*> saved_designs;
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virtual ~DesignPass() {
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for (auto &it : saved_designs)
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delete it.second;
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saved_designs.clear();
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}
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" design -reset\n");
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log("\n");
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log("Clear the current design.\n");
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log("\n");
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log("\n");
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log(" design -save <name>\n");
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log("\n");
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log("Save the current design under the given name.\n");
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log("\n");
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log("\n");
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log(" design -load <name>\n");
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log("\n");
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log("Reset the current design and load the design previously saved under the given\n");
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log("name.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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bool got_mode = false;
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bool reset_mode = false;
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std::string save_name, load_name;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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std::string arg = args[argidx];
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if (!got_mode && arg == "-reset") {
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got_mode = true;
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reset_mode = true;
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continue;
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}
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if (arg == "-save" && argidx+1 < args.size()) {
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got_mode = true;
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save_name = args[++argidx];
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continue;
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}
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if (arg == "-load" && argidx+1 < args.size()) {
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got_mode = true;
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load_name = args[++argidx];
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if (saved_designs.count(load_name) == 0)
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log_cmd_error("No saved design '%s' found!\n", load_name.c_str());
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continue;
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}
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}
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extra_args(args, argidx, design, false);
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if (!got_mode)
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cmd_error(args, argidx, "Missing mode argument (-reset, -save, or -load).");
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if (reset_mode || !load_name.empty())
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{
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for (auto &it : design->modules)
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delete it.second;
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design->modules.clear();
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design->selection_stack.clear();
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design->selection_vars.clear();
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design->selected_active_module.clear();
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design->selection_stack.push_back(RTLIL::Selection());
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}
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if (!save_name.empty())
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{
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RTLIL::Design *design_copy = new RTLIL::Design;
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for (auto &it : design->modules)
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design_copy->modules[it.first] = it.second->clone();
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design_copy->selection_stack = design->selection_stack;
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design_copy->selection_vars = design->selection_vars;
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design_copy->selected_active_module = design->selected_active_module;
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if (saved_designs.count(save_name))
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delete saved_designs.at(save_name);
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saved_designs[save_name] = design_copy;
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}
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if (!load_name.empty())
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{
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RTLIL::Design *saved_design = saved_designs.at(load_name);
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for (auto &it : saved_design->modules)
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design->modules[it.first] = it.second->clone();
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design->selection_stack = saved_design->selection_stack;
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design->selection_vars = saved_design->selection_vars;
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design->selected_active_module = saved_design->selected_active_module;
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}
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}
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} DesignPass;
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