mirror of https://github.com/YosysHQ/yosys.git
108 lines
2.6 KiB
Plaintext
108 lines
2.6 KiB
Plaintext
pattern dffmux
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state <IdString> cemuxAB rstmuxBA
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state <SigSpec> sigD
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match dff
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select dff->type == $dff
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select GetSize(port(dff, \D)) > 1
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endmatch
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match rstmux
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select rstmux->type == $mux
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select GetSize(port(rstmux, \Y)) > 1
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index <SigSpec> port(rstmux, \Y) === port(dff, \D)
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choice <IdString> BA {\B, \A}
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select port(rstmux, BA).is_fully_const()
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set rstmuxBA BA
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optional
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endmatch
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code sigD
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if (rstmux)
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sigD = port(rstmux, rstmuxBA == \B ? \A : \B);
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else
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sigD = port(dff, \D);
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endcode
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match cemux
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select cemux->type == $mux
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select GetSize(port(cemux, \Y)) > 1
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index <SigSpec> port(cemux, \Y) === sigD
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choice <IdString> AB {\A, \B}
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index <SigSpec> port(cemux, AB) === port(dff, \Q)
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set cemuxAB AB
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endmatch
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code
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SigSpec D = port(cemux, cemuxAB == \A ? \B : \A);
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SigSpec Q = port(dff, \Q);
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Const rst;
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if (rstmux)
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rst = port(rstmux, rstmuxBA).as_const();
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int width = GetSize(D);
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if (D[width-1] == D[width-2]) {
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did_something = true;
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SigBit sign = D[width-1];
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bool is_signed = sign.wire;
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int i;
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for (i = width-1; i >= 2; i--) {
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if (!is_signed) {
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module->connect(Q[i], sign);
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if (D[i-1] != sign || (rst.size() && rst[i-1] != rst[width-1]))
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break;
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}
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else {
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module->connect(Q[i], Q[i-1]);
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if (D[i-2] != sign || (rst.size() && rst[i-1] != rst[width-1]))
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break;
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}
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}
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cemux->connections_.at(\A).remove(i, width-i);
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cemux->connections_.at(\B).remove(i, width-i);
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cemux->connections_.at(\Y).remove(i, width-i);
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cemux->fixup_parameters();
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dff->connections_.at(\D).remove(i, width-i);
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dff->connections_.at(\Q).remove(i, width-i);
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dff->fixup_parameters();
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log("dffcemux pattern in %s: dff=%s, cemux=%s; removed top %d bits.\n", log_id(module), log_id(dff), log_id(cemux), width-i);
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accept;
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}
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else {
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int count = 0;
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for (int i = width-1; i >= 0; i--) {
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if (D[i].wire)
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continue;
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Wire *w = Q[i].wire;
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auto it = w->attributes.find(\init);
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State init;
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if (it != w->attributes.end())
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init = it->second[Q[i].offset];
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else
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init = State::Sx;
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if (init == State::Sx || init == D[i].data) {
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count++;
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module->connect(Q[i], D[i]);
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cemux->connections_.at(\A).remove(i);
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cemux->connections_.at(\B).remove(i);
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cemux->connections_.at(\Y).remove(i);
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dff->connections_.at(\D).remove(i);
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dff->connections_.at(\Q).remove(i);
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}
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}
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if (count > 0) {
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did_something = true;
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cemux->fixup_parameters();
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dff->fixup_parameters();
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log("dffcemux pattern in %s: dff=%s, cemux=%s; removed %d constant bits.\n", log_id(module), log_id(dff), log_id(cemux), count);
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}
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accept;
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}
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endcode
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