Eddie Hung e18aeda7ed Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards ... Just like Verilog...		2020-01-27 14:02:13 -08:00
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cmds	autoname: do not autoname ports	2020-01-14 10:13:29 -08:00
equiv	xilinx: Add xilinx_dffopt pass (#1557)	2019-12-18 13:43:43 +01:00
fsm	fsm_detect: Add a cache to avoid excessive CPU usage for big mux networks.	2020-01-14 22:49:20 +01:00
hierarchy	Remove submod changes	2019-12-30 14:56:14 -08:00
memory	Cleanup	2019-12-17 00:25:08 -08:00
opt	Fix opt_expr.eqneq.cmpzero debug print	2019-12-15 20:40:38 +01:00
pmgen	Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards	2020-01-27 14:02:13 -08:00
proc	proc_dlatch: Add error handling for incorrect always_(ff|latch|comb) usage	2019-11-21 20:46:41 +00:00
sat	Add fminit pass	2020-01-09 21:22:54 +01:00
techmap	abc9_ops: add comments	2020-01-27 11:18:21 -08:00
tests	Document (* gentb_skip *) attr for test_autotb	2019-09-18 12:41:35 -07:00