yosys/passes
whitequark e0def9e4d9 memory_map: add -attr option, to respect inference attributes.
Before this commit, memory_map (which is always a part of a synth
script) would always pick up any $mem cell that was not processed
by a preceding pass and lower it down to $dff/$mux cells.
This is undesirable for two reasons:
  * If there is an explicit inference attribute set on a $mem cell,
    e.g. (* ram_block *), then it is arguably incorrect to map such
    a memory to $dff/$mux cells.
  * If memory_map tries to lower a memory that was intended to
    be mapped to a large BRAM, it often takes extraordinarily long
    time to finish, produces an extremely large log file, and outputs
    an unusable design.

After this commit, properly invoked memory_map will not map any
memory that has an explicit inference attribute specified, solving
the first issue, and alleviating the second. The default behavior
is not changed.
2020-04-03 05:51:40 +00:00
..
cmds redirect fuser stderr to /dev/null 2020-01-28 10:02:41 +01:00
equiv xilinx: Add xilinx_dffopt pass (#1557) 2019-12-18 13:43:43 +01:00
fsm fsm_detect: Add a cache to avoid excessive CPU usage for big mux networks. 2020-01-14 22:49:20 +01:00
hierarchy sv: Improve handling of wildcard port connections 2020-02-02 16:12:33 +00:00
memory memory_map: add -attr option, to respect inference attributes. 2020-04-03 05:51:40 +00:00
opt Merge pull request #1576 from YosysHQ/eddie/opt_merge_init 2020-02-05 14:56:26 -08:00
pmgen Merge pull request #1657 from YosysHQ/dave/xilinx-dsp-multonly 2020-02-02 14:53:32 +00:00
proc proc_dlatch: Add error handling for incorrect always_(ff|latch|comb) usage 2019-11-21 20:46:41 +00:00
sat Merge pull request #1638 from YosysHQ/eddie/fix1631 2020-02-05 19:31:18 +01:00
techmap abc9_ops: -reintegrate to use derived_type for box_ports 2020-02-05 14:46:48 -08:00
tests Document (* gentb_skip *) attr for test_autotb 2019-09-18 12:41:35 -07:00