Clifford Wolf 7a66b38c3e Added test cases for sat command		2014-02-04 13:43:34 +01:00
..
asicworld	Fixed undef behavior in tests/asicworld/code_verilog_tutorial_fsm_full_tb.v	2013-05-24 15:15:59 +02:00
hana	added more .gitignore files (make test)	2013-01-05 11:35:52 +01:00
i2c_bench	Renamed stdcells_sim.v to simcells.v and fixed blackbox.v	2013-11-24 20:44:00 +01:00
k68_vltor	Now only use value from "initial" when no matching "always" block is found	2013-03-31 11:51:12 +02:00
sat	Added test cases for sat command	2014-02-04 13:43:34 +01:00
simple	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	2014-02-03 13:01:45 +01:00
tools	Replaced isim with xsim in tests/tools/autotest.sh, removed xst support	2014-02-03 13:00:55 +01:00