mirror of https://github.com/YosysHQ/yosys.git
52 lines
935 B
Plaintext
52 lines
935 B
Plaintext
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read_verilog -formal <<EOT
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module gate (input [2:0] A, B, C, D, X, output reg [2:0] Y);
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always @*
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(* parallel_case *)
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casez (X)
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3'b??1: Y = A;
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3'b?1?: Y = B;
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3'b1??: Y = C;
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3'b000: Y = D;
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endcase
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endmodule
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EOT
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## Examle usage for "pmuxtree" and "muxcover"
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proc
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pmuxtree
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techmap
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muxcover -mux4
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splitnets -ports
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clean
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# show
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## Equivalence checking
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read_verilog -formal <<EOT
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module gold (input [2:0] A, B, C, D, X, output reg [2:0] Y);
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always @*
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casez (X)
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3'b001: Y = A;
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3'b010: Y = B;
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3'b100: Y = C;
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3'b000: Y = D;
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default: Y = 'bx;
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endcase
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endmodule
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EOT
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proc
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splitnets -ports
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techmap -map +/simcells.v t:$_MUX4_
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equiv_make gold gate equiv
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hierarchy -top equiv
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equiv_simple -undef
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equiv_status -assert
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