mirror of https://github.com/YosysHQ/yosys.git
16 lines
567 B
Plaintext
16 lines
567 B
Plaintext
read_verilog -sv asserts_seq.v
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hierarchy; proc; opt; async2sync
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sat -verify -prove-asserts -tempinduct -seq 1 test_001
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sat -falsify -prove-asserts -tempinduct -seq 1 test_002
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sat -falsify -prove-asserts -tempinduct -seq 1 test_003
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sat -falsify -prove-asserts -tempinduct -seq 1 test_004
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sat -verify -prove-asserts -tempinduct -seq 1 test_005
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sat -verify -prove-asserts -seq 2 test_001
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sat -falsify -prove-asserts -seq 2 test_002
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sat -falsify -prove-asserts -seq 2 test_003
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sat -falsify -prove-asserts -seq 2 test_004
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sat -verify -prove-asserts -seq 2 test_005
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