yosys/frontends/verilog
Sylvain Munaut 58fb2ac818 verilog_parser: Properly handle recursion when processing attributes
Fixes #737

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-12-14 12:48:00 +01:00
..
.gitignore Add "make coverage" 2018-08-27 14:22:21 +02:00
Makefile.inc Add "make coverage" 2018-08-27 14:22:21 +02:00
const2ast.cc Convert more log_error() to log_file_error() where possible. 2018-07-20 09:37:44 -07:00
preproc.cc Support SystemVerilog `` extension for macros 2018-05-17 00:09:56 -04:00
verilog_frontend.cc Add "read_verilog -noassert -noassume -assert-assumes" 2018-09-24 20:51:16 +02:00
verilog_frontend.h Add "read_verilog -noassert -noassume -assert-assumes" 2018-09-24 20:51:16 +02:00
verilog_lexer.l Merge pull request #659 from rubund/sv_interfaces 2018-10-18 10:58:47 +02:00
verilog_parser.y verilog_parser: Properly handle recursion when processing attributes 2018-12-14 12:48:00 +01:00