mirror of https://github.com/YosysHQ/yosys.git
13 lines
318 B
Plaintext
13 lines
318 B
Plaintext
read_verilog <<EOF
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module top(input [16:0] a, input [16:0] b, input [16:0] c, input [16:0] d, output reg [33:0] o);
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always @(*)
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o <= (a * b) + (c * d);
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endmodule
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EOF
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synth_quicklogic -family qlf_k6n10f -dspv2 -run :coarse
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read_verilog +/quicklogic/qlf_k6n10f/dsp_sim.v
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prep -top top -flatten
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opt_clean -purge
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dump
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