mirror of https://github.com/YosysHQ/yosys.git
18 lines
312 B
Plaintext
18 lines
312 B
Plaintext
read_verilog <<EOF
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module top(input [16:0] a, input [16:0] b, output reg [33:0] o, input clk, input [2:0] j);
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reg [16:0] ar;
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reg [16:0] br;
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always @(posedge clk) begin
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ar <= a;
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br <= b;
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o <= {ar * br, j};
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end
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endmodule
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EOF
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synth_quicklogic -family qlf_k6n10f -dspv2 -run :coarse
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check
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opt_clean
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dump
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