mirror of https://github.com/YosysHQ/yosys.git
24 lines
585 B
Plaintext
24 lines
585 B
Plaintext
read_verilog <<EOF
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module top(input signed [16:0] ar, input signed [16:0] ai, input signed [16:0] br, input signed [16:0] bi, output reg signed [33:0] qr, output reg signed [33:0] qi, input clk);
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reg signed [33:0] rr, ri, ir, ii;
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always @(posedge clk) begin
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rr <= ar * br;
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ri <= ar * bi;
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ir <= ai * br;
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ii <= ai * bi;
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qr <= rr - ii;
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qi <= ir + ri;
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end
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endmodule
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EOF
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synth_quicklogic -family qlf_k6n10f -dspv2 -run :coarse
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check -assert
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read_verilog +/quicklogic/qlf_k6n10f/dsp_sim.v
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prep -top top -flatten
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opt_clean -purge
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opt -full
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opt_clean -purge
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check -assert
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dump
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