riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
yosys/frontends/ast
History
Clifford Wolf 7f1a1759d7 Added "read_verilog -nomeminit" and "nomeminit" attribute 2015-02-14 11:21:12 +01:00
..
Makefile.inc Added Verilog/AST support for DPI functions (dpi_call() still unimplemented) 2014-08-21 12:43:51 +02:00
ast.cc Added "read_verilog -nomeminit" and "nomeminit" attribute 2015-02-14 11:21:12 +01:00
ast.h Added "read_verilog -nomeminit" and "nomeminit" attribute 2015-02-14 11:21:12 +01:00
dpicall.cc Renamed SIZE() to GetSize() because of name collision on Win32 2014-10-10 17:07:24 +02:00
genrtlil.cc Creating $meminit cells in verilog front-end 2015-02-14 10:49:30 +01:00
simplify.cc Added "read_verilog -nomeminit" and "nomeminit" attribute 2015-02-14 11:21:12 +01:00