mirror of https://github.com/YosysHQ/yosys.git
571 lines
20 KiB
C++
571 lines
20 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/rtlil.h"
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/celltypes.h"
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#include "kernel/log.h"
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#include <string>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct Smt2Worker
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{
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CellTypes ct;
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SigMap sigmap;
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RTLIL::Module *module;
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bool bvmode;
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int idcounter;
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std::vector<std::string> decls, trans;
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std::map<RTLIL::SigBit, RTLIL::Cell*> bit_driver;
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std::set<RTLIL::Cell*> exported_cells;
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std::map<RTLIL::SigBit, std::pair<int, int>> fcache;
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std::map<int, int> bvsizes;
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Smt2Worker(RTLIL::Module *module, bool bvmode) : ct(module->design), sigmap(module), module(module), bvmode(bvmode), idcounter(0)
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{
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decls.push_back(stringf("(declare-sort |%s_s| 0)\n", log_id(module)));
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for (auto cell : module->cells())
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for (auto &conn : cell->connections()) {
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bool is_input = ct.cell_input(cell->type, conn.first);
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bool is_output = ct.cell_output(cell->type, conn.first);
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if (is_output && !is_input)
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for (auto bit : sigmap(conn.second)) {
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if (bit_driver.count(bit))
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log_error("Found multiple drivers for %s.\n", log_signal(bit));
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bit_driver[bit] = cell;
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}
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else if (is_output || !is_input)
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log_error("Unsupported or unknown directionality on port %s of cell %s.%s (%s).\n",
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log_id(conn.first), log_id(module), log_id(cell), log_id(cell->type));
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}
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}
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void register_bool(RTLIL::SigBit bit, int id)
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{
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sigmap.apply(bit);
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log_assert(fcache.count(bit) == 0);
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fcache[bit] = std::pair<int, int>(id, -1);
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}
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void register_bv(RTLIL::SigSpec sig, int id)
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{
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log_assert(bvmode);
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sigmap.apply(sig);
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log_assert(bvsizes.count(id) == 0);
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bvsizes[id] = GetSize(sig);
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for (int i = 0; i < GetSize(sig); i++) {
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log_assert(fcache.count(sig[i]) == 0);
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fcache[sig[i]] = std::pair<int, int>(id, i);
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}
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}
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void register_boolvec(RTLIL::SigSpec sig, int id)
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{
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log_assert(bvmode);
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sigmap.apply(sig);
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register_bool(sig[0], id);
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for (int i = 1; i < GetSize(sig); i++)
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sigmap.add(sig[i], RTLIL::State::S0);
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}
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std::string get_bool(RTLIL::SigBit bit, const char *state_name = "state")
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{
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sigmap.apply(bit);
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if (bit.wire == nullptr)
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return bit == RTLIL::State::S1 ? "true" : "false";
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if (bit_driver.count(bit))
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export_cell(bit_driver.at(bit));
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sigmap.apply(bit);
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if (fcache.count(bit) == 0) {
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decls.push_back(stringf("(declare-fun |%s#%d| (|%s_s|) Bool) ; %s\n",
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log_id(module), idcounter, log_id(module), log_signal(bit)));
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register_bool(bit, idcounter++);
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}
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auto f = fcache.at(bit);
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if (f.second >= 0)
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return stringf("(= ((_ extract %d %d) (|%s#%d| %s)) #b1)", f.second, f.second, log_id(module), f.first, state_name);
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return stringf("(|%s#%d| %s)", log_id(module), f.first, state_name);
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}
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std::string get_bool(RTLIL::SigSpec sig, const char *state_name = "state")
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{
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return get_bool(sig.to_single_sigbit(), state_name);
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}
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std::string get_bv(RTLIL::SigSpec sig, const char *state_name = "state")
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{
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log_assert(bvmode);
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sigmap.apply(sig);
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std::vector<std::string> subexpr;
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for (auto bit : sig)
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if (bit_driver.count(bit))
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export_cell(bit_driver.at(bit));
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sigmap.apply(sig);
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for (int i = 0, j = 1; i < GetSize(sig); i += j, j = 1)
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{
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if (sig[i].wire == nullptr) {
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while (i+j < GetSize(sig) && sig[i+j].wire == nullptr) j++;
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subexpr.push_back("#b");
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for (int k = i+j-1; k >= i; k--)
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subexpr.back() += sig[k] == RTLIL::State::S1 ? "1" : "0";
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continue;
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}
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if (fcache.count(sig[i]) && fcache.at(sig[i]).second == -1) {
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subexpr.push_back(stringf("(ite %s #b1 #b0)", get_bool(sig[i], state_name).c_str()));
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continue;
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}
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if (fcache.count(sig[i])) {
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auto t1 = fcache.at(sig[i]);
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while (i+j < GetSize(sig)) {
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if (fcache.count(sig[i+j]) == 0)
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break;
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auto t2 = fcache.at(sig[i+j]);
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if (t1.first != t2.first)
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break;
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if (t1.second+j != t2.second)
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break;
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j++;
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}
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if (t1.second == 0 && j == bvsizes.at(t1.first))
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subexpr.push_back(stringf("(|%s#%d| state)", log_id(module), t1.first));
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else
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subexpr.push_back(stringf("((_ extract %d %d) (|%s#%d| state))", t1.second + j - 1, t1.second, log_id(module), t1.first));
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continue;
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}
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std::set<RTLIL::SigBit> seen_bits = { sig[i] };
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while (i+j < GetSize(sig) && sig[i+j].wire && !fcache.count(sig[i+j]) && !seen_bits.count(sig[i+j]))
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seen_bits.insert(sig[i+j]), j++;
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decls.push_back(stringf("(declare-fun |%s#%d| (|%s_s|) (_ BitVec %d)) ; %s\n",
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log_id(module), idcounter, log_id(module), j, log_signal(sig.extract(i, j))));
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subexpr.push_back(stringf("(|%s#%d| state)", log_id(module), idcounter));
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register_bv(sig.extract(i, j), idcounter++);
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}
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if (GetSize(subexpr) > 1) {
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std::string expr = "(concat";
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for (int i = GetSize(subexpr)-1; i >= 0; i--)
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expr += " " + subexpr[i];
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return expr + ")";
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} else {
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log_assert(GetSize(subexpr) == 1);
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return subexpr[0];
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}
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}
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void export_gate(RTLIL::Cell *cell, std::string expr)
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{
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RTLIL::SigBit bit = sigmap(cell->getPort("\\Y").to_single_sigbit());
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std::string processed_expr;
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for (char ch : expr) {
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if (ch == 'A') processed_expr += get_bool(cell->getPort("\\A"));
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else if (ch == 'B') processed_expr += get_bool(cell->getPort("\\B"));
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else if (ch == 'C') processed_expr += get_bool(cell->getPort("\\C"));
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else if (ch == 'D') processed_expr += get_bool(cell->getPort("\\D"));
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else if (ch == 'S') processed_expr += get_bool(cell->getPort("\\S"));
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else processed_expr += ch;
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}
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decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) Bool %s) ; %s\n",
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log_id(module), idcounter, log_id(module), processed_expr.c_str(), log_signal(bit)));
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register_bool(bit, idcounter++);
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return;
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}
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void export_bvop(RTLIL::Cell *cell, std::string expr, char type = 0)
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{
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RTLIL::SigSpec sig_a, sig_b;
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RTLIL::SigSpec sig_y = sigmap(cell->getPort("\\Y"));
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bool is_signed = cell->getParam("\\A_SIGNED").as_bool();
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int width = GetSize(sig_y);
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if (type == 's' || type == 'd' || type == 'b') {
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width = std::max(width, GetSize(cell->getPort("\\A")));
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width = std::max(width, GetSize(cell->getPort("\\B")));
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}
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if (cell->hasPort("\\A")) {
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sig_a = cell->getPort("\\A");
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sig_a.extend_u0(width, is_signed);
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}
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if (cell->hasPort("\\B")) {
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sig_b = cell->getPort("\\B");
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sig_b.extend_u0(width, is_signed && !(type == 's'));
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}
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std::string processed_expr;
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for (char ch : expr) {
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if (ch == 'A') processed_expr += get_bv(sig_a);
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else if (ch == 'B') processed_expr += get_bv(sig_b);
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else if (ch == 'L') processed_expr += is_signed ? "a" : "l";
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else if (ch == 'U') processed_expr += is_signed ? "s" : "u";
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else processed_expr += ch;
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}
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if (width != GetSize(sig_y) && type != 'b')
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processed_expr = stringf("((_ extract %d 0) %s)", GetSize(sig_y)-1, processed_expr.c_str());
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if (type == 'b') {
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decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) Bool %s) ; %s\n",
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log_id(module), idcounter, log_id(module), processed_expr.c_str(), log_signal(sig_y)));
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register_boolvec(sig_y, idcounter++);
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} else {
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decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
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log_id(module), idcounter, log_id(module), GetSize(sig_y), processed_expr.c_str(), log_signal(sig_y)));
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register_bv(sig_y, idcounter++);
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}
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return;
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}
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void export_reduce(RTLIL::Cell *cell, std::string expr, bool identity_val)
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{
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RTLIL::SigSpec sig_y = sigmap(cell->getPort("\\Y"));
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std::string processed_expr;
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for (char ch : expr)
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if (ch == 'A' || ch == 'B') {
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RTLIL::SigSpec sig = sigmap(cell->getPort(stringf("\\%c", ch)));
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for (auto bit : sig)
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processed_expr += " " + get_bool(bit);
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if (GetSize(sig) == 1)
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processed_expr += identity_val ? " true" : " false";
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} else
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processed_expr += ch;
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decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) Bool %s) ; %s\n",
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log_id(module), idcounter, log_id(module), processed_expr.c_str(), log_signal(sig_y)));
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register_boolvec(sig_y, idcounter++);
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return;
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}
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void export_cell(RTLIL::Cell *cell)
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{
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if (exported_cells.count(cell))
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return;
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exported_cells.insert(cell);
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if (cell->type == "$_DFF_P_" || cell->type == "$_DFF_N_")
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{
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std::string expr_d = get_bool(cell->getPort("\\D"));
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std::string expr_q = get_bool(cell->getPort("\\Q"), "next_state");
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trans.push_back(stringf(" (= %s %s)\n", expr_d.c_str(), expr_q.c_str()));
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return;
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}
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if (cell->type == "$_BUF_") return export_gate(cell, "A");
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if (cell->type == "$_NOT_") return export_gate(cell, "(not A)");
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if (cell->type == "$_AND_") return export_gate(cell, "(and A B)");
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if (cell->type == "$_NAND_") return export_gate(cell, "(not (and A B))");
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if (cell->type == "$_OR_") return export_gate(cell, "(or A B)");
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if (cell->type == "$_NOR_") return export_gate(cell, "(not (or A B))");
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if (cell->type == "$_XOR_") return export_gate(cell, "(xor A B)");
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if (cell->type == "$_XNOR_") return export_gate(cell, "(not (xor A B))");
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if (cell->type == "$_MUX_") return export_gate(cell, "(ite S B A)");
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if (cell->type == "$_AOI3_") return export_gate(cell, "(not (or (and A B) C))");
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if (cell->type == "$_OAI3_") return export_gate(cell, "(not (and (or A B) C))");
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if (cell->type == "$_AOI4_") return export_gate(cell, "(not (or (and A B) (and C D)))");
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if (cell->type == "$_OAI4_") return export_gate(cell, "(not (and (or A B) (or C D)))");
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// FIXME: $lut $assert
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if (!bvmode)
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log_error("Unsupported cell type %s for cell %s.%s. (Maybe this cell type would be supported in -bv mode?)\n",
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log_id(cell->type), log_id(module), log_id(cell));
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if (cell->type == "$dff")
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{
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std::string expr_d = get_bv(cell->getPort("\\D"));
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std::string expr_q = get_bv(cell->getPort("\\Q"), "next_state");
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trans.push_back(stringf(" (= %s %s)\n", expr_d.c_str(), expr_q.c_str()));
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return;
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}
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if (cell->type == "$and") return export_bvop(cell, "(bvand A B)");
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if (cell->type == "$or") return export_bvop(cell, "(bvor A B)");
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if (cell->type == "$xor") return export_bvop(cell, "(bvxor A B)");
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if (cell->type == "$xnor") return export_bvop(cell, "(bvxnor A B)");
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if (cell->type == "$shl") return export_bvop(cell, "(bvshl A B)", 's');
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if (cell->type == "$shr") return export_bvop(cell, "(bvlshr A B)", 's');
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if (cell->type == "$sshl") return export_bvop(cell, "(bvshl A B)", 's');
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if (cell->type == "$sshr") return export_bvop(cell, "(bvLshr A B)", 's');
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// FIXME: $shift $shiftx
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if (cell->type == "$lt") return export_bvop(cell, "(bvUlt A B)", 'b');
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if (cell->type == "$le") return export_bvop(cell, "(bvUle A B)", 'b');
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if (cell->type == "$ge") return export_bvop(cell, "(bvUge A B)", 'b');
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if (cell->type == "$gt") return export_bvop(cell, "(bvUgt A B)", 'b');
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if (cell->type == "$ne") return export_bvop(cell, "(distinct A B)", 'b');
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if (cell->type == "$nex") return export_bvop(cell, "(distinct A B)", 'b');
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if (cell->type == "$eq") return export_bvop(cell, "(= A B)", 'b');
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if (cell->type == "$eqx") return export_bvop(cell, "(= A B)", 'b');
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if (cell->type == "$not") return export_bvop(cell, "(bvnot A)");
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if (cell->type == "$pos") return export_bvop(cell, "A");
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if (cell->type == "$neg") return export_bvop(cell, "(bvneg A)");
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if (cell->type == "$add") return export_bvop(cell, "(bvadd A B)");
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if (cell->type == "$sub") return export_bvop(cell, "(bvsub A B)");
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if (cell->type == "$mul") return export_bvop(cell, "(bvmul A B)");
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if (cell->type == "$div") return export_bvop(cell, "(bvUdiv A B)", 'd');
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if (cell->type == "$mod") return export_bvop(cell, "(bvUrem A B)", 'd');
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if (cell->type == "$reduce_and") return export_reduce(cell, "(and A)", true);
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if (cell->type == "$reduce_or") return export_reduce(cell, "(or A)", false);
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if (cell->type == "$reduce_xor") return export_reduce(cell, "(xor A)", false);
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if (cell->type == "$reduce_xnor") return export_reduce(cell, "(not (xor A))", false);
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if (cell->type == "$reduce_bool") return export_reduce(cell, "(or A)", false);
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if (cell->type == "$logic_not") return export_reduce(cell, "(not (or A))", false);
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if (cell->type == "$logic_and") return export_reduce(cell, "(and (or A) (or B))", false);
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if (cell->type == "$logic_or") return export_reduce(cell, "(or A B)", false);
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if (cell->type == "$mux" || cell->type == "$pmux")
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{
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int width = GetSize(cell->getPort("\\Y"));
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std::string processed_expr = get_bv(cell->getPort("\\A"));
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RTLIL::SigSpec sig_b = cell->getPort("\\B");
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RTLIL::SigSpec sig_s = cell->getPort("\\S");
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get_bv(sig_b);
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get_bv(sig_s);
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for (int i = 0; i < GetSize(sig_s); i++)
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processed_expr = stringf("(ite %s %s %s)", get_bool(sig_s[i]).c_str(),
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get_bv(sig_b.extract(i*width, width)).c_str(), processed_expr.c_str());
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RTLIL::SigSpec sig = sigmap(cell->getPort("\\Y"));
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decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
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log_id(module), idcounter, log_id(module), width, processed_expr.c_str(), log_signal(sig)));
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register_bv(sig, idcounter++);
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return;
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}
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// FIXME: $slice $concat
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log_error("Unsupported cell type %s for cell %s.%s.\n",
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log_id(cell->type), log_id(module), log_id(cell));
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}
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void run()
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{
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for (auto wire : module->wires())
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if (wire->port_id || wire->get_bool_attribute("\\keep")) {
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RTLIL::SigSpec sig = sigmap(wire);
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if (bvmode && GetSize(sig) > 1) {
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decls.push_back(stringf("(define-fun |%s_n %s| ((state |%s_s|)) (_ BitVec %d) %s)\n",
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log_id(module), log_id(wire), log_id(module), GetSize(sig), get_bv(sig).c_str()));
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} else {
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for (int i = 0; i < GetSize(sig); i++)
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if (GetSize(sig) > 1)
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decls.push_back(stringf("(define-fun |%s_n %s %d| ((state |%s_s|)) Bool %s)\n",
|
|
log_id(module), log_id(wire), i, log_id(module), get_bool(sig[i]).c_str()));
|
|
else
|
|
decls.push_back(stringf("(define-fun |%s_n %s| ((state |%s_s|)) Bool %s)\n",
|
|
log_id(module), log_id(wire), log_id(module), get_bool(sig[i]).c_str()));
|
|
}
|
|
}
|
|
}
|
|
|
|
void write(std::ostream &f)
|
|
{
|
|
for (auto it : decls)
|
|
f << it;
|
|
|
|
f << stringf("(define-fun |%s_t| ((state |%s_s|) (next_state |%s_s|)) Bool ", log_id(module), log_id(module), log_id(module));
|
|
if (GetSize(trans) > 1) {
|
|
f << "(and\n";
|
|
for (auto it : trans)
|
|
f << it;
|
|
f << "))";
|
|
} else
|
|
if (GetSize(trans) == 1)
|
|
f << "\n" + trans.front() + ")";
|
|
else
|
|
f << "true)";
|
|
f << stringf(" ; end of module %s\n", log_id(module));
|
|
}
|
|
};
|
|
|
|
struct Smt2Backend : public Backend {
|
|
Smt2Backend() : Backend("smt2", "write design to SMT-LIBv2 file") { }
|
|
virtual void help()
|
|
{
|
|
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
|
log("\n");
|
|
log(" write_smt2 [options] [filename]\n");
|
|
log("\n");
|
|
log("Write a SMT-LIBv2 [1] description of the current design. For a module with name\n");
|
|
log("'<mod>' this will declare the sort '<mod>_s' (state of the module) and the the\n");
|
|
log("function '<mod>_t' (state transition function).\n");
|
|
log("\n");
|
|
log("The '<mod>_s' sort represents a module state. Additional '<mod>_n' functions\n");
|
|
log("are provided that can be used to access the values of the signals in the module.\n");
|
|
log("Only ports, and signals with the 'keep' attribute set are made available via\n");
|
|
log("such functions. Without the -bv option, multi-bit wires are exported as\n");
|
|
log("separate functions of type Bool for the individual bits. With the -bv option\n");
|
|
log("multi-bit wires are exported as single functions of type BitVec.\n");
|
|
log("\n");
|
|
log("The '<mod>_t' function evaluates to 'true' when the given pair of states\n");
|
|
log("describes a valid state transition.\n");
|
|
log("\n");
|
|
log(" -bv\n");
|
|
log(" enable support for BitVec (FixedSizeBitVectors theory). with this\n");
|
|
log(" option set multi-bit wires are represented using the BitVec sort and\n");
|
|
log(" support for coarse grain cells (incl. arithmetic) is enabled.\n");
|
|
log("\n");
|
|
log(" -tpl <template_file>\n");
|
|
log(" use the given template file. the line containing only the token '%%%%'\n");
|
|
log(" is replaced with the regular output of this command.\n");
|
|
log("\n");
|
|
log("[1] For more information on SMT-LIBv2 visit http://smt-lib.org/ or read David\n");
|
|
log("R. Cok's tutorial: http://www.grammatech.com/resources/smt/SMTLIBTutorial.pdf\n");
|
|
log("\n");
|
|
log("---------------------------------------------------------------------------\n");
|
|
log("\n");
|
|
log("Example:\n");
|
|
log("\n");
|
|
log("Consider the following module (test.v). We want to prove that the output can\n");
|
|
log("never transition from a non-zero value to a zero value.\n");
|
|
log("\n");
|
|
log(" module test(input clk, output reg [3:0] y);\n");
|
|
log(" always @(posedge clk)\n");
|
|
log(" y <= (y << 1) | ^y;\n");
|
|
log(" endmodule\n");
|
|
log("\n");
|
|
log("For this proof we create the following template (test.tpl).\n");
|
|
log("\n");
|
|
log(" ; we need QF_UFBV for this poof\n");
|
|
log(" (set-logic QF_UFBV)\n");
|
|
log("\n");
|
|
log(" ; insert the auto-generated code here\n");
|
|
log(" %%%%\n");
|
|
log("\n");
|
|
log(" ; declare two state variables s1 and s2\n");
|
|
log(" (declare-fun s1 () test_s)\n");
|
|
log(" (declare-fun s2 () test_s)\n");
|
|
log("\n");
|
|
log(" ; state s2 is the successor of state s1\n");
|
|
log(" (assert (test_t s1 s2))\n");
|
|
log("\n");
|
|
log(" ; we are looking for a model with y non-zero in s1\n");
|
|
log(" (assert (distinct (|test_n y| s1) #b0000))\n");
|
|
log("\n");
|
|
log(" ; we are looking for a model with y zero in s2\n");
|
|
log(" (assert (= (|test_n y| s2) #b0000))\n");
|
|
log("\n");
|
|
log(" ; is there such a model?\n");
|
|
log(" (check-sat)\n");
|
|
log("\n");
|
|
log("The following yosys script will create a 'test.smt2' file for our proof:\n");
|
|
log("\n");
|
|
log(" read_verilog test.v\n");
|
|
log(" hierarchy; proc; techmap; opt -fast\n");
|
|
log(" write_smt2 -bv -tpl test.tpl test.smt2\n");
|
|
log("\n");
|
|
log("Running 'cvc4 test.smt2' will print 'unsat' because y can never transition\n");
|
|
log("from non-zero to zero in the test design.\n");
|
|
log("\n");
|
|
}
|
|
virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
|
|
{
|
|
std::ifstream template_f;
|
|
bool bvmode = false;
|
|
|
|
log_header("Executing SMT2 backend.\n");
|
|
|
|
size_t argidx;
|
|
for (argidx = 1; argidx < args.size(); argidx++)
|
|
{
|
|
if (args[argidx] == "-tpl" && argidx+1 < args.size()) {
|
|
template_f.open(args[++argidx]);
|
|
if (template_f.fail())
|
|
log_error("Can't open template file `%s'.\n", args[argidx].c_str());
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-bv") {
|
|
bvmode = true;
|
|
continue;
|
|
}
|
|
break;
|
|
}
|
|
extra_args(f, filename, args, argidx);
|
|
|
|
if (template_f.is_open()) {
|
|
std::string line;
|
|
while (std::getline(template_f, line)) {
|
|
int indent = 0;
|
|
while (indent < GetSize(line) && (line[indent] == ' ' || line[indent] == '\t'))
|
|
indent++;
|
|
if (line.substr(indent, 2) == "%%")
|
|
break;
|
|
*f << line << std::endl;
|
|
}
|
|
}
|
|
|
|
*f << stringf("; SMT-LIBv2 description generated by %s\n", yosys_version_str);
|
|
|
|
for (auto module : design->modules())
|
|
{
|
|
if (module->get_bool_attribute("\\blackbox") || module->has_memories_warn() || module->has_processes_warn())
|
|
continue;
|
|
|
|
log("Creating SMT-LIBv2 representation of module %s.\n", log_id(module));
|
|
|
|
Smt2Worker worker(module, bvmode);
|
|
worker.run();
|
|
worker.write(*f);
|
|
}
|
|
|
|
*f << stringf("; end of yosys output\n");
|
|
|
|
if (template_f.is_open()) {
|
|
std::string line;
|
|
while (std::getline(template_f, line))
|
|
*f << line << std::endl;
|
|
}
|
|
}
|
|
} Smt2Backend;
|
|
|
|
PRIVATE_NAMESPACE_END
|