mirror of https://github.com/YosysHQ/yosys.git
53 lines
747 B
Plaintext
53 lines
747 B
Plaintext
read_rtlil <<EOT
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module \pdk_not
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wire input 1 \A
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wire output 2 \Y
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cell $_NOT_ \not
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connect \A \A
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connect \Y \Y
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end
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end
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module \pdk_buf
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wire input 1 \A
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wire output 2 \Y
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cell $_BUF_ \buf
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connect \A \A
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connect \Y \Y
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end
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end
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module \top
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wire input 1 \A
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wire output 2 \Y
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wire \w
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cell \pdk_buf \buf
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connect \A \A
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connect \Y \w
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end
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cell \pdk_not \not
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connect \A \w
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connect \Y \Y
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end
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end
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EOT
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cellmatch -lut_attrs *
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select -set buffers a:lut=2'b10 %m
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select -set inverters a:lut=2'b01 %m
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select -assert-count 1 t:@buffers t:pdk_buf %i
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select -assert-count 0 t:@buffers t:pdk_not %i
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select -assert-count 0 t:@inverters t:pdk_buf %i
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select -assert-count 1 t:@inverters t:pdk_not %i
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