mirror of https://github.com/YosysHQ/yosys.git
2cab4ff173
This makes tests/verilog/dynamic_range_lhs.v pass, after ensuring that nowrshmsk is actually tested. Stride is extracted from indexing of two-dimensional packed arrays and variable slices on the form dst[i*stride +: width] = src, and is used to optimize the generated CASE block. Also uses less confusing variable names for indexing of lhs wires. |
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| .. | ||
| Makefile.inc | ||
| ast.cc | ||
| ast.h | ||
| ast_binding.cc | ||
| ast_binding.h | ||
| dpicall.cc | ||
| genrtlil.cc | ||
| simplify.cc | ||