mirror of https://github.com/YosysHQ/yosys.git
448 lines
14 KiB
C++
448 lines
14 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef CELLTYPES_H
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#define CELLTYPES_H
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#include <kernel/yosys.h>
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YOSYS_NAMESPACE_BEGIN
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struct CellType
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{
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RTLIL::IdString type;
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pool<RTLIL::IdString> inputs, outputs;
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bool is_evaluable;
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};
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struct CellTypes
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{
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dict<RTLIL::IdString, CellType> cell_types;
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CellTypes()
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{
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}
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CellTypes(RTLIL::Design *design)
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{
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setup(design);
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}
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void setup(RTLIL::Design *design = NULL)
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{
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if (design)
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setup_design(design);
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setup_internals();
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setup_internals_mem();
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setup_stdcells();
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setup_stdcells_mem();
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}
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void setup_type(RTLIL::IdString type, const pool<RTLIL::IdString> &inputs, const pool<RTLIL::IdString> &outputs, bool is_evaluable = false)
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{
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CellType ct = {type, inputs, outputs, is_evaluable};
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cell_types[ct.type] = ct;
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}
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void setup_module(RTLIL::Module *module)
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{
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pool<RTLIL::IdString> inputs, outputs;
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for (RTLIL::IdString wire_name : module->ports) {
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RTLIL::Wire *wire = module->wire(wire_name);
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if (wire->port_input)
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inputs.insert(wire->name);
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if (wire->port_output)
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outputs.insert(wire->name);
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}
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setup_type(module->name, inputs, outputs);
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}
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void setup_design(RTLIL::Design *design)
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{
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for (auto module : design->modules())
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setup_module(module);
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}
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void setup_internals()
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{
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std::vector<RTLIL::IdString> unary_ops = {
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"$not", "$pos", "$neg",
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"$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool",
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"$logic_not", "$slice", "$lut", "$sop"
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};
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std::vector<RTLIL::IdString> binary_ops = {
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"$and", "$or", "$xor", "$xnor",
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"$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx",
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"$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt",
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"$add", "$sub", "$mul", "$div", "$mod", "$pow",
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"$logic_and", "$logic_or", "$concat", "$macc"
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};
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IdString A = "\\A", B = "\\B", S = "\\S", Y = "\\Y";
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IdString P = "\\P", G = "\\G", C = "\\C", X = "\\X";
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IdString BI = "\\BI", CI = "\\CI", CO = "\\CO", EN = "\\EN";
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for (auto type : unary_ops)
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setup_type(type, {A}, {Y}, true);
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for (auto type : binary_ops)
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setup_type(type, {A, B}, {Y}, true);
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for (auto type : std::vector<RTLIL::IdString>({"$mux", "$pmux"}))
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setup_type(type, {A, B, S}, {Y}, true);
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setup_type("$lcu", {P, G, CI}, {CO}, true);
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setup_type("$alu", {A, B, CI, BI}, {X, Y, CO}, true);
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setup_type("$fa", {A, B, C}, {X, Y}, true);
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setup_type("$tribuf", {A, EN}, {Y}, true);
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setup_type("$assert", {A, EN}, pool<RTLIL::IdString>(), true);
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setup_type("$assume", {A, EN}, pool<RTLIL::IdString>(), true);
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setup_type("$predict", {A, EN}, pool<RTLIL::IdString>(), true);
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setup_type("$initstate", pool<RTLIL::IdString>(), {Y}, true);
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setup_type("$anyconst", pool<RTLIL::IdString>(), {Y}, true);
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setup_type("$aconst", pool<RTLIL::IdString>(), {Y}, true);
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setup_type("$equiv", {A, B}, {Y}, true);
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}
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void setup_internals_mem()
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{
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IdString SET = "\\SET", CLR = "\\CLR", CLK = "\\CLK", ARST = "\\ARST", EN = "\\EN";
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IdString Q = "\\Q", D = "\\D", ADDR = "\\ADDR", DATA = "\\DATA", RD_EN = "\\RD_EN";
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IdString RD_CLK = "\\RD_CLK", RD_ADDR = "\\RD_ADDR", WR_CLK = "\\WR_CLK", WR_EN = "\\WR_EN";
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IdString WR_ADDR = "\\WR_ADDR", WR_DATA = "\\WR_DATA", RD_DATA = "\\RD_DATA";
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IdString CTRL_IN = "\\CTRL_IN", CTRL_OUT = "\\CTRL_OUT";
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setup_type("$sr", {SET, CLR}, {Q});
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setup_type("$dff", {CLK, D}, {Q});
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setup_type("$dffe", {CLK, EN, D}, {Q});
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setup_type("$dffsr", {CLK, SET, CLR, D}, {Q});
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setup_type("$adff", {CLK, ARST, D}, {Q});
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setup_type("$dlatch", {EN, D}, {Q});
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setup_type("$dlatchsr", {EN, SET, CLR, D}, {Q});
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setup_type("$memrd", {CLK, EN, ADDR}, {DATA});
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setup_type("$memwr", {CLK, EN, ADDR, DATA}, pool<RTLIL::IdString>());
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setup_type("$meminit", {ADDR, DATA}, pool<RTLIL::IdString>());
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setup_type("$mem", {RD_CLK, RD_EN, RD_ADDR, WR_CLK, WR_EN, WR_ADDR, WR_DATA}, {RD_DATA});
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setup_type("$fsm", {CLK, ARST, CTRL_IN}, {CTRL_OUT});
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}
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void setup_stdcells()
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{
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IdString A = "\\A", B = "\\B", C = "\\C", D = "\\D";
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IdString E = "\\E", F = "\\F", G = "\\G", H = "\\H";
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IdString I = "\\I", J = "\\J", K = "\\K", L = "\\L";
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IdString M = "\\I", N = "\\N", O = "\\O", P = "\\P";
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IdString S = "\\S", T = "\\T", U = "\\U", V = "\\V";
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IdString Y = "\\Y";
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setup_type("$_BUF_", {A}, {Y}, true);
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setup_type("$_NOT_", {A}, {Y}, true);
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setup_type("$_AND_", {A, B}, {Y}, true);
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setup_type("$_NAND_", {A, B}, {Y}, true);
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setup_type("$_OR_", {A, B}, {Y}, true);
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setup_type("$_NOR_", {A, B}, {Y}, true);
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setup_type("$_XOR_", {A, B}, {Y}, true);
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setup_type("$_XNOR_", {A, B}, {Y}, true);
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setup_type("$_MUX_", {A, B, S}, {Y}, true);
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setup_type("$_MUX4_", {A, B, C, D, S, T}, {Y}, true);
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setup_type("$_MUX8_", {A, B, C, D, E, F, G, H, S, T, U}, {Y}, true);
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setup_type("$_MUX16_", {A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V}, {Y}, true);
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setup_type("$_AOI3_", {A, B, C}, {Y}, true);
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setup_type("$_OAI3_", {A, B, C}, {Y}, true);
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setup_type("$_AOI4_", {A, B, C, D}, {Y}, true);
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setup_type("$_OAI4_", {A, B, C, D}, {Y}, true);
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setup_type("$_TBUF_", {A, E}, {Y}, true);
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}
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void setup_stdcells_mem()
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{
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IdString S = "\\S", R = "\\R", C = "\\C";
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IdString D = "\\D", Q = "\\Q", E = "\\E";
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std::vector<char> list_np = {'N', 'P'}, list_01 = {'0', '1'};
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for (auto c1 : list_np)
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for (auto c2 : list_np)
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setup_type(stringf("$_SR_%c%c_", c1, c2), {S, R}, {Q});
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for (auto c1 : list_np)
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setup_type(stringf("$_DFF_%c_", c1), {C, D}, {Q});
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for (auto c1 : list_np)
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for (auto c2 : list_np)
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setup_type(stringf("$_DFFE_%c%c_", c1, c2), {C, D, E}, {Q});
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for (auto c1 : list_np)
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for (auto c2 : list_np)
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for (auto c3 : list_01)
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setup_type(stringf("$_DFF_%c%c%c_", c1, c2, c3), {C, R, D}, {Q});
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for (auto c1 : list_np)
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for (auto c2 : list_np)
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for (auto c3 : list_np)
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setup_type(stringf("$_DFFSR_%c%c%c_", c1, c2, c3), {C, S, R, D}, {Q});
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for (auto c1 : list_np)
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setup_type(stringf("$_DLATCH_%c_", c1), {E, D}, {Q});
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for (auto c1 : list_np)
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for (auto c2 : list_np)
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for (auto c3 : list_np)
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setup_type(stringf("$_DLATCHSR_%c%c%c_", c1, c2, c3), {E, S, R, D}, {Q});
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}
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void clear()
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{
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cell_types.clear();
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}
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bool cell_known(RTLIL::IdString type)
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{
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return cell_types.count(type) != 0;
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}
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bool cell_output(RTLIL::IdString type, RTLIL::IdString port)
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{
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auto it = cell_types.find(type);
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return it != cell_types.end() && it->second.outputs.count(port) != 0;
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}
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bool cell_input(RTLIL::IdString type, RTLIL::IdString port)
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{
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auto it = cell_types.find(type);
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return it != cell_types.end() && it->second.inputs.count(port) != 0;
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}
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bool cell_evaluable(RTLIL::IdString type)
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{
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auto it = cell_types.find(type);
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return it != cell_types.end() && it->second.is_evaluable;
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}
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static RTLIL::Const eval_not(RTLIL::Const v)
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{
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for (auto &bit : v.bits)
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if (bit == RTLIL::S0) bit = RTLIL::S1;
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else if (bit == RTLIL::S1) bit = RTLIL::S0;
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return v;
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}
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static RTLIL::Const eval(RTLIL::IdString type, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
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{
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if (type == "$sshr" && !signed1)
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type = "$shr";
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if (type == "$sshl" && !signed1)
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type = "$shl";
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if (type != "$sshr" && type != "$sshl" && type != "$shr" && type != "$shl" && type != "$shift" && type != "$shiftx" &&
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type != "$pos" && type != "$neg" && type != "$not") {
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if (!signed1 || !signed2)
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signed1 = false, signed2 = false;
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}
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#define HANDLE_CELL_TYPE(_t) if (type == "$" #_t) return const_ ## _t(arg1, arg2, signed1, signed2, result_len);
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HANDLE_CELL_TYPE(not)
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HANDLE_CELL_TYPE(and)
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HANDLE_CELL_TYPE(or)
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HANDLE_CELL_TYPE(xor)
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HANDLE_CELL_TYPE(xnor)
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HANDLE_CELL_TYPE(reduce_and)
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HANDLE_CELL_TYPE(reduce_or)
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HANDLE_CELL_TYPE(reduce_xor)
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HANDLE_CELL_TYPE(reduce_xnor)
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HANDLE_CELL_TYPE(reduce_bool)
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HANDLE_CELL_TYPE(logic_not)
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HANDLE_CELL_TYPE(logic_and)
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HANDLE_CELL_TYPE(logic_or)
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HANDLE_CELL_TYPE(shl)
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HANDLE_CELL_TYPE(shr)
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HANDLE_CELL_TYPE(sshl)
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HANDLE_CELL_TYPE(sshr)
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HANDLE_CELL_TYPE(shift)
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HANDLE_CELL_TYPE(shiftx)
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HANDLE_CELL_TYPE(lt)
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HANDLE_CELL_TYPE(le)
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HANDLE_CELL_TYPE(eq)
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HANDLE_CELL_TYPE(ne)
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HANDLE_CELL_TYPE(eqx)
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HANDLE_CELL_TYPE(nex)
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HANDLE_CELL_TYPE(ge)
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HANDLE_CELL_TYPE(gt)
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HANDLE_CELL_TYPE(add)
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HANDLE_CELL_TYPE(sub)
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HANDLE_CELL_TYPE(mul)
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HANDLE_CELL_TYPE(div)
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HANDLE_CELL_TYPE(mod)
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HANDLE_CELL_TYPE(pow)
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HANDLE_CELL_TYPE(pos)
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HANDLE_CELL_TYPE(neg)
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#undef HANDLE_CELL_TYPE
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if (type == "$_BUF_")
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return arg1;
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if (type == "$_NOT_")
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return eval_not(arg1);
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if (type == "$_AND_")
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return const_and(arg1, arg2, false, false, 1);
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if (type == "$_NAND_")
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return eval_not(const_and(arg1, arg2, false, false, 1));
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if (type == "$_OR_")
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return const_or(arg1, arg2, false, false, 1);
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if (type == "$_NOR_")
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return eval_not(const_and(arg1, arg2, false, false, 1));
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if (type == "$_XOR_")
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return const_xor(arg1, arg2, false, false, 1);
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if (type == "$_XNOR_")
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return const_xnor(arg1, arg2, false, false, 1);
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log_abort();
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}
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static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2)
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{
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if (cell->type == "$slice") {
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RTLIL::Const ret;
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int width = cell->parameters.at("\\Y_WIDTH").as_int();
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int offset = cell->parameters.at("\\OFFSET").as_int();
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ret.bits.insert(ret.bits.end(), arg1.bits.begin()+offset, arg1.bits.begin()+offset+width);
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return ret;
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}
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if (cell->type == "$concat") {
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RTLIL::Const ret = arg1;
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ret.bits.insert(ret.bits.end(), arg2.bits.begin(), arg2.bits.end());
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return ret;
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}
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if (cell->type == "$lut")
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{
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int width = cell->parameters.at("\\WIDTH").as_int();
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std::vector<RTLIL::State> t = cell->parameters.at("\\LUT").bits;
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while (GetSize(t) < (1 << width))
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t.push_back(RTLIL::S0);
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t.resize(1 << width);
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for (int i = width-1; i >= 0; i--) {
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RTLIL::State sel = arg1.bits.at(i);
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std::vector<RTLIL::State> new_t;
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if (sel == RTLIL::S0)
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new_t = std::vector<RTLIL::State>(t.begin(), t.begin() + GetSize(t)/2);
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else if (sel == RTLIL::S1)
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new_t = std::vector<RTLIL::State>(t.begin() + GetSize(t)/2, t.end());
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else
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for (int j = 0; j < GetSize(t)/2; j++)
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new_t.push_back(t[j] == t[j + GetSize(t)/2] ? t[j] : RTLIL::Sx);
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t.swap(new_t);
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}
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log_assert(GetSize(t) == 1);
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return t;
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}
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if (cell->type == "$sop")
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{
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int width = cell->parameters.at("\\WIDTH").as_int();
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int depth = cell->parameters.at("\\DEPTH").as_int();
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std::vector<RTLIL::State> t = cell->parameters.at("\\TABLE").bits;
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while (GetSize(t) < width*depth*2)
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t.push_back(RTLIL::S0);
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RTLIL::State default_ret = State::S0;
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for (int i = 0; i < depth; i++)
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{
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bool match = true;
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bool match_x = true;
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for (int j = 0; j < width; j++) {
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RTLIL::State a = arg1.bits.at(j);
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if (t.at(2*width*i + 2*j + 0) == State::S1) {
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if (a == State::S1) match_x = false;
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if (a != State::S0) match = false;
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}
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if (t.at(2*width*i + 2*j + 1) == State::S1) {
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if (a == State::S0) match_x = false;
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if (a != State::S1) match = false;
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}
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}
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if (match)
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return State::S1;
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if (match_x)
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default_ret = State::Sx;
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}
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return default_ret;
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}
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bool signed_a = cell->parameters.count("\\A_SIGNED") > 0 && cell->parameters["\\A_SIGNED"].as_bool();
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bool signed_b = cell->parameters.count("\\B_SIGNED") > 0 && cell->parameters["\\B_SIGNED"].as_bool();
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int result_len = cell->parameters.count("\\Y_WIDTH") > 0 ? cell->parameters["\\Y_WIDTH"].as_int() : -1;
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return eval(cell->type, arg1, arg2, signed_a, signed_b, result_len);
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}
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static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3)
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{
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if (cell->type.in("$mux", "$pmux", "$_MUX_")) {
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RTLIL::Const ret = arg1;
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for (size_t i = 0; i < arg3.bits.size(); i++)
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if (arg3.bits[i] == RTLIL::State::S1) {
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std::vector<RTLIL::State> bits(arg2.bits.begin() + i*arg1.bits.size(), arg2.bits.begin() + (i+1)*arg1.bits.size());
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ret = RTLIL::Const(bits);
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}
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return ret;
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}
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if (cell->type == "$_AOI3_")
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return eval_not(const_or(const_and(arg1, arg2, false, false, 1), arg3, false, false, 1));
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if (cell->type == "$_OAI3_")
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return eval_not(const_and(const_or(arg1, arg2, false, false, 1), arg3, false, false, 1));
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log_assert(arg3.bits.size() == 0);
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return eval(cell, arg1, arg2);
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}
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static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, const RTLIL::Const &arg4)
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{
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if (cell->type == "$_AOI4_")
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return eval_not(const_or(const_and(arg1, arg2, false, false, 1), const_and(arg3, arg4, false, false, 1), false, false, 1));
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if (cell->type == "$_OAI4_")
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return eval_not(const_and(const_or(arg1, arg2, false, false, 1), const_and(arg3, arg4, false, false, 1), false, false, 1));
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log_assert(arg4.bits.size() == 0);
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return eval(cell, arg1, arg2, arg3);
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}
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};
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// initialized by yosys_setup()
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extern CellTypes yosys_celltypes;
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YOSYS_NAMESPACE_END
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#endif
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