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d9fa1e5a1d
yosys
/
tests
/
asicworld
/
code_tidbits_wire_example.v
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module
wire_example
(
a
,
b
,
y
)
;
input
a
,
b
;
output
y
;
wire
a
,
b
,
y
;
assign
y
=
a
&
b
;
endmodule
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