riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
yosys/tests/arch/intel_alm
History
Marcelina Kościelnicka 18806f1ef6 memory_bram: Reuse extract_rdff helper for make_outreg. 
Also properly skip read ports with init value or reset when not making
use of make_outreg.  Proper support for matching those will land later.
 		2021-05-25 22:42:03 +02:00
..
.gitignore Add missing .gitignore file 2020-06-04 22:25:47 +02:00
add_sub.ys intel_alm: Fix illegal carry chains 2021-05-15 22:37:06 +01:00
adffs.ys intel_alm: Add global buffer insertion 2021-05-15 22:37:06 +01:00
blockram.ys intel_alm: Add global buffer insertion 2021-05-15 22:37:06 +01:00
counter.ys intel_alm: Fix illegal carry chains 2021-05-15 22:37:06 +01:00
dffs.ys intel_alm: Add global buffer insertion 2021-05-15 22:37:06 +01:00
fsm.ys intel_alm: Add global buffer insertion 2021-05-15 22:37:06 +01:00
logic.ys intel_alm: Add global buffer insertion 2021-05-15 22:37:06 +01:00
lutram.ys memory_bram: Reuse extract_rdff helper for make_outreg. 2021-05-25 22:42:03 +02:00
mul.ys intel_alm: Add global buffer insertion 2021-05-15 22:37:06 +01:00
mux.ys intel_alm: Add global buffer insertion 2021-05-15 22:37:06 +01:00
quartus_ice.ys intel_alm: Add global buffer insertion 2021-05-15 22:37:06 +01:00
run-test.sh tests: Centralize test collection and Makefile generation 2020-09-21 15:07:02 +02:00
shifter.ys intel_alm: Add global buffer insertion 2021-05-15 22:37:06 +01:00
tribuf.ys intel_alm: Add global buffer insertion 2021-05-15 22:37:06 +01:00