mirror of https://github.com/YosysHQ/yosys.git
93 lines
2.9 KiB
C++
93 lines
2.9 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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#include "passes/pmgen/ice40_wrapcarry_pm.h"
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void create_ice40_wrapcarry(ice40_wrapcarry_pm &pm)
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{
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auto &st = pm.st_ice40_wrapcarry;
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#if 0
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log("\n");
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log("carry: %s\n", log_id(st.carry, "--"));
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log("lut: %s\n", log_id(st.lut, "--"));
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#endif
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log(" replacing SB_LUT + SB_CARRY with $__ICE40_CARRY_WRAPPER cell.\n");
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Cell *cell = pm.module->addCell(NEW_ID, "$__ICE40_CARRY_WRAPPER");
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pm.module->swap_names(cell, st.carry);
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cell->setPort("\\A", st.carry->getPort("\\I0"));
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cell->setPort("\\B", st.carry->getPort("\\I1"));
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cell->setPort("\\CI", st.carry->getPort("\\CI"));
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cell->setPort("\\CO", st.carry->getPort("\\CO"));
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cell->setPort("\\I0", st.lut->getPort("\\I0"));
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cell->setPort("\\I3", st.lut->getPort("\\I3"));
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cell->setPort("\\O", st.lut->getPort("\\O"));
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cell->setParam("\\LUT", st.lut->getParam("\\LUT_INIT"));
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cell->attributes = std::move(st.carry->attributes);
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pm.autoremove(st.carry);
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pm.autoremove(st.lut);
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}
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struct Ice40WrapCarryPass : public Pass {
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Ice40WrapCarryPass() : Pass("ice40_wrapcarry", "iCE40: wrap carries") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" ice40_wrapcarry [selection]\n");
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log("\n");
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log("Wrap manually instantiated SB_CARRY cells, along with their associated SB_LUTs,\n");
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log("into an internal $__ICE40_CARRY_WRAPPER cell for preservation across technology\n");
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log("mapping.");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing ICE40_WRAPCARRY pass (wrap carries).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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// if (args[argidx] == "-singleton") {
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// singleton_mode = true;
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// continue;
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// }
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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ice40_wrapcarry_pm(module, module->selected_cells()).run_ice40_wrapcarry(create_ice40_wrapcarry);
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}
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} Ice40WrapCarryPass;
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PRIVATE_NAMESPACE_END
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