mirror of https://github.com/YosysHQ/yosys.git
63b9df8693
- *_en is split into *_ce (clock enable) and *_aload (async load aka latch gate enable), so both can be present at once - has_d is removed - has_gclk is added (to have a clear marker for $ff) - d_is_const and val_d leftovers are removed - async2sync, clk2fflogic, opt_dff are updated to operate correctly on FFs with async load |
||
---|---|---|
.. | ||
Makefile.inc | ||
verilog_backend.cc |