mirror of https://github.com/YosysHQ/yosys.git
287 lines
8.7 KiB
C++
287 lines
8.7 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/bitpattern.h"
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#include "kernel/log.h"
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#include <sstream>
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#include <stdlib.h>
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#include <stdio.h>
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#include <assert.h>
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static RTLIL::SigSpec find_any_lvalue(const RTLIL::CaseRule *cs)
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{
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for (auto &action : cs->actions) {
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if (action.first.size())
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return action.first;
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}
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for (auto sw : cs->switches)
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for (auto cs2 : sw->cases) {
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RTLIL::SigSpec sig = find_any_lvalue(cs2);
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if (sig.size())
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return sig;
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}
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return RTLIL::SigSpec();
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}
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static void extract_core_signal(const RTLIL::CaseRule *cs, RTLIL::SigSpec &sig)
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{
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for (auto &action : cs->actions) {
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RTLIL::SigSpec lvalue = action.first.extract(sig);
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if (lvalue.size())
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sig = lvalue;
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}
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for (auto sw : cs->switches)
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for (auto cs2 : sw->cases)
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extract_core_signal(cs2, sig);
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}
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static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SwitchRule *sw)
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{
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std::stringstream sstr;
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sstr << "$procmux$" << (RTLIL::autoidx++);
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RTLIL::Wire *cmp_wire = mod->addWire(sstr.str() + "_CMP", 0);
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for (auto comp : compare)
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{
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RTLIL::SigSpec sig = signal;
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// get rid of don't-care bits
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assert(sig.size() == comp.size());
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for (int i = 0; i < comp.size(); i++)
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if (comp[i] == RTLIL::State::Sa) {
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sig.remove(i);
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comp.remove(i--);
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}
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if (comp.size() == 0)
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return RTLIL::SigSpec();
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if (sig.size() == 1 && comp == RTLIL::SigSpec(1,1))
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{
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mod->connect(RTLIL::SigSig(RTLIL::SigSpec(cmp_wire, cmp_wire->width++), sig));
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}
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else
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{
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// create compare cell
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RTLIL::Cell *eq_cell = mod->addCell(stringf("%s_CMP%d", sstr.str().c_str(), cmp_wire->width), "$eq");
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eq_cell->attributes = sw->attributes;
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eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
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eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(0);
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eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.size());
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eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(comp.size());
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eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
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eq_cell->set("\\A", sig);
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eq_cell->set("\\B", comp);
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eq_cell->set("\\Y", RTLIL::SigSpec(cmp_wire, cmp_wire->width++));
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}
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}
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RTLIL::Wire *ctrl_wire;
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if (cmp_wire->width == 1)
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{
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ctrl_wire = cmp_wire;
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}
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else
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{
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ctrl_wire = mod->addWire(sstr.str() + "_CTRL");
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// reduce cmp vector to one logic signal
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RTLIL::Cell *any_cell = mod->addCell(sstr.str() + "_ANY", "$reduce_or");
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any_cell->attributes = sw->attributes;
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any_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
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any_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cmp_wire->width);
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any_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
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any_cell->set("\\A", cmp_wire);
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any_cell->set("\\Y", RTLIL::SigSpec(ctrl_wire));
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}
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return RTLIL::SigSpec(ctrl_wire);
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}
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static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::SigSpec else_signal, RTLIL::Cell *&last_mux_cell, RTLIL::SwitchRule *sw)
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{
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assert(when_signal.size() == else_signal.size());
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std::stringstream sstr;
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sstr << "$procmux$" << (RTLIL::autoidx++);
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// the trivial cases
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if (compare.size() == 0 || when_signal == else_signal)
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return when_signal;
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// compare results
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RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw);
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if (ctrl_sig.size() == 0)
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return when_signal;
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assert(ctrl_sig.size() == 1);
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// prepare multiplexer output signal
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RTLIL::Wire *result_wire = mod->addWire(sstr.str() + "_Y", when_signal.size());
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// create the multiplexer itself
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RTLIL::Cell *mux_cell = mod->addCell(sstr.str(), "$mux");
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mux_cell->attributes = sw->attributes;
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mux_cell->parameters["\\WIDTH"] = RTLIL::Const(when_signal.size());
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mux_cell->set("\\A", else_signal);
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mux_cell->set("\\B", when_signal);
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mux_cell->set("\\S", ctrl_sig);
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mux_cell->set("\\Y", RTLIL::SigSpec(result_wire));
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last_mux_cell = mux_cell;
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return RTLIL::SigSpec(result_wire);
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}
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static void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw)
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{
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assert(last_mux_cell != NULL);
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assert(when_signal.size() == last_mux_cell->get("\\A").size());
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RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw);
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assert(ctrl_sig.size() == 1);
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last_mux_cell->type = "$pmux";
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RTLIL::SigSpec new_s = last_mux_cell->get("\\S");
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new_s.append(ctrl_sig);
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last_mux_cell->set("\\S", new_s);
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RTLIL::SigSpec new_b = last_mux_cell->get("\\B");
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new_b.append(when_signal);
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last_mux_cell->set("\\B", new_b);
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last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->get("\\S").size();
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}
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static RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs, const RTLIL::SigSpec &sig, const RTLIL::SigSpec &defval)
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{
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RTLIL::SigSpec result = defval;
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for (auto &action : cs->actions) {
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sig.replace(action.first, action.second, &result);
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action.first.remove2(sig, &action.second);
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}
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for (auto sw : cs->switches)
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{
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// detect groups of parallel cases
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std::vector<int> pgroups(sw->cases.size());
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if (!sw->get_bool_attribute("\\parallel_case")) {
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BitPatternPool pool(sw->signal.size());
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bool extra_group_for_next_case = false;
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for (size_t i = 0; i < sw->cases.size(); i++) {
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RTLIL::CaseRule *cs2 = sw->cases[i];
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if (i != 0) {
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pgroups[i] = pgroups[i-1];
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if (extra_group_for_next_case) {
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pgroups[i] = pgroups[i-1]+1;
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extra_group_for_next_case = false;
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}
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for (auto pat : cs2->compare)
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if (!pat.is_fully_const() || !pool.has_all(pat))
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pgroups[i] = pgroups[i-1]+1;
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if (cs2->compare.empty())
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pgroups[i] = pgroups[i-1]+1;
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if (pgroups[i] != pgroups[i-1])
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pool = BitPatternPool(sw->signal.size());
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}
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for (auto pat : cs2->compare)
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if (!pat.is_fully_const())
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extra_group_for_next_case = true;
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else
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pool.take(pat);
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}
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}
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// evaluate in reverse order to give the first entry the top priority
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RTLIL::SigSpec initial_val = result;
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RTLIL::Cell *last_mux_cell = NULL;
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for (size_t i = 0; i < sw->cases.size(); i++) {
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int case_idx = sw->cases.size() - i - 1;
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RTLIL::CaseRule *cs2 = sw->cases[case_idx];
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RTLIL::SigSpec value = signal_to_mux_tree(mod, cs2, sig, initial_val);
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if (last_mux_cell && pgroups[case_idx] == pgroups[case_idx+1])
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append_pmux(mod, sw->signal, cs2->compare, value, last_mux_cell, sw);
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else
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result = gen_mux(mod, sw->signal, cs2->compare, value, result, last_mux_cell, sw);
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}
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}
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return result;
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}
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static void proc_mux(RTLIL::Module *mod, RTLIL::Process *proc)
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{
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bool first = true;
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while (1)
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{
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RTLIL::SigSpec sig = find_any_lvalue(&proc->root_case);
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if (sig.size() == 0)
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break;
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if (first) {
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log("Creating decoders for process `%s.%s'.\n", mod->name.c_str(), proc->name.c_str());
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first = false;
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}
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extract_core_signal(&proc->root_case, sig);
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log(" creating decoder for signal `%s'.\n", log_signal(sig));
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RTLIL::SigSpec value = signal_to_mux_tree(mod, &proc->root_case, sig, RTLIL::SigSpec(RTLIL::State::Sx, sig.size()));
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mod->connect(RTLIL::SigSig(sig, value));
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}
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}
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struct ProcMuxPass : public Pass {
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ProcMuxPass() : Pass("proc_mux", "convert decision trees to multiplexers") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" proc_mux [selection]\n");
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log("\n");
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log("This pass converts the decision trees in processes (originating from if-else\n");
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log("and case statements) to trees of multiplexer cells.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header("Executing PROC_MUX pass (convert decision trees to multiplexers).\n");
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extra_args(args, 1, design);
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for (auto mod : design->modules())
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if (design->selected(mod))
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for (auto &proc_it : mod->processes)
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if (design->selected(mod, proc_it.second))
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proc_mux(mod, proc_it.second);
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}
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} ProcMuxPass;
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