mirror of https://github.com/YosysHQ/yosys.git
455 lines
14 KiB
C++
455 lines
14 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/log.h"
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#include <stdlib.h>
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#include <assert.h>
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#include <stdio.h>
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#include <string.h>
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extern void simplemap_get_mappers(std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers);
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static void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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RTLIL::SigSpec sig_a = cell->get("\\A");
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RTLIL::SigSpec sig_y = cell->get("\\Y");
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sig_a.extend(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
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for (int i = 0; i < SIZE(sig_y); i++) {
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RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_");
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gate->set("\\A", sig_a[i]);
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gate->set("\\Y", sig_y[i]);
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}
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}
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static void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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RTLIL::SigSpec sig_a = cell->get("\\A");
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RTLIL::SigSpec sig_y = cell->get("\\Y");
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sig_a.extend(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
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module->connect(RTLIL::SigSig(sig_y, sig_a));
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}
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static void simplemap_bu0(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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RTLIL::SigSpec sig_a = cell->get("\\A");
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RTLIL::SigSpec sig_y = cell->get("\\Y");
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sig_a.extend_u0(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
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module->connect(RTLIL::SigSig(sig_y, sig_a));
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}
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static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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RTLIL::SigSpec sig_a = cell->get("\\A");
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RTLIL::SigSpec sig_b = cell->get("\\B");
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RTLIL::SigSpec sig_y = cell->get("\\Y");
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sig_a.extend_u0(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
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sig_b.extend_u0(SIZE(sig_y), cell->parameters.at("\\B_SIGNED").as_bool());
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if (cell->type == "$xnor")
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{
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RTLIL::SigSpec sig_t = module->addWire(NEW_ID, SIZE(sig_y));
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for (int i = 0; i < SIZE(sig_y); i++) {
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RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_");
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gate->set("\\A", sig_t[i]);
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gate->set("\\Y", sig_y[i]);
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}
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sig_y = sig_t;
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}
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std::string gate_type;
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if (cell->type == "$and") gate_type = "$_AND_";
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if (cell->type == "$or") gate_type = "$_OR_";
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if (cell->type == "$xor") gate_type = "$_XOR_";
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if (cell->type == "$xnor") gate_type = "$_XOR_";
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log_assert(!gate_type.empty());
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for (int i = 0; i < SIZE(sig_y); i++) {
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RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
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gate->set("\\A", sig_a[i]);
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gate->set("\\B", sig_b[i]);
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gate->set("\\Y", sig_y[i]);
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}
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}
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static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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RTLIL::SigSpec sig_a = cell->get("\\A");
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RTLIL::SigSpec sig_y = cell->get("\\Y");
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if (sig_y.size() == 0)
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return;
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if (sig_a.size() == 0) {
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if (cell->type == "$reduce_and") module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
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if (cell->type == "$reduce_or") module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
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if (cell->type == "$reduce_xor") module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
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if (cell->type == "$reduce_xnor") module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
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if (cell->type == "$reduce_bool") module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
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return;
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}
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if (sig_y.size() > 1) {
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module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1)));
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sig_y = sig_y.extract(0, 1);
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}
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std::string gate_type;
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if (cell->type == "$reduce_and") gate_type = "$_AND_";
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if (cell->type == "$reduce_or") gate_type = "$_OR_";
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if (cell->type == "$reduce_xor") gate_type = "$_XOR_";
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if (cell->type == "$reduce_xnor") gate_type = "$_XOR_";
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if (cell->type == "$reduce_bool") gate_type = "$_OR_";
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log_assert(!gate_type.empty());
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RTLIL::Cell *last_output_cell = NULL;
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while (sig_a.size() > 1)
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{
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RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig_a.size() / 2);
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for (int i = 0; i < sig_a.size(); i += 2)
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{
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if (i+1 == sig_a.size()) {
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sig_t.append(sig_a[i]);
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continue;
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}
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RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
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gate->set("\\A", sig_a[i]);
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gate->set("\\B", sig_a[i+1]);
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gate->set("\\Y", sig_t[i/2]);
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last_output_cell = gate;
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}
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sig_a = sig_t;
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}
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if (cell->type == "$reduce_xnor") {
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RTLIL::SigSpec sig_t = module->addWire(NEW_ID);
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RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_");
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gate->set("\\A", sig_a);
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gate->set("\\Y", sig_t);
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last_output_cell = gate;
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sig_a = sig_t;
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}
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if (last_output_cell == NULL) {
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module->connect(RTLIL::SigSig(sig_y, sig_a));
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} else {
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last_output_cell->set("\\Y", sig_y);
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}
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}
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static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig)
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{
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while (sig.size() > 1)
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{
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RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig.size() / 2);
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for (int i = 0; i < sig.size(); i += 2)
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{
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if (i+1 == sig.size()) {
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sig_t.append(sig[i]);
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continue;
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}
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RTLIL::Cell *gate = module->addCell(NEW_ID, "$_OR_");
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gate->set("\\A", sig[i]);
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gate->set("\\B", sig[i+1]);
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gate->set("\\Y", sig_t[i/2]);
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}
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sig = sig_t;
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}
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if (sig.size() == 0)
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sig = RTLIL::SigSpec(0, 1);
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}
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static void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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RTLIL::SigSpec sig_a = cell->get("\\A");
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logic_reduce(module, sig_a);
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RTLIL::SigSpec sig_y = cell->get("\\Y");
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if (sig_y.size() == 0)
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return;
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if (sig_y.size() > 1) {
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module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1)));
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sig_y = sig_y.extract(0, 1);
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}
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RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_");
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gate->set("\\A", sig_a);
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gate->set("\\Y", sig_y);
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}
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static void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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RTLIL::SigSpec sig_a = cell->get("\\A");
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logic_reduce(module, sig_a);
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RTLIL::SigSpec sig_b = cell->get("\\B");
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logic_reduce(module, sig_b);
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RTLIL::SigSpec sig_y = cell->get("\\Y");
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if (sig_y.size() == 0)
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return;
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if (sig_y.size() > 1) {
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module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1)));
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sig_y = sig_y.extract(0, 1);
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}
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std::string gate_type;
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if (cell->type == "$logic_and") gate_type = "$_AND_";
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if (cell->type == "$logic_or") gate_type = "$_OR_";
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log_assert(!gate_type.empty());
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RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
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gate->set("\\A", sig_a);
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gate->set("\\B", sig_b);
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gate->set("\\Y", sig_y);
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}
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static void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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RTLIL::SigSpec sig_a = cell->get("\\A");
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RTLIL::SigSpec sig_b = cell->get("\\B");
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RTLIL::SigSpec sig_y = cell->get("\\Y");
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for (int i = 0; i < SIZE(sig_y); i++) {
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RTLIL::Cell *gate = module->addCell(NEW_ID, "$_MUX_");
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gate->set("\\A", sig_a[i]);
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gate->set("\\B", sig_b[i]);
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gate->set("\\S", cell->get("\\S"));
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gate->set("\\Y", sig_y[i]);
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}
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}
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static void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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int offset = cell->parameters.at("\\OFFSET").as_int();
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RTLIL::SigSpec sig_a = cell->get("\\A");
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RTLIL::SigSpec sig_y = cell->get("\\Y");
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module->connect(RTLIL::SigSig(sig_y, sig_a.extract(offset, sig_y.size())));
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}
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static void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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RTLIL::SigSpec sig_ab = cell->get("\\A");
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sig_ab.append(cell->get("\\B"));
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RTLIL::SigSpec sig_y = cell->get("\\Y");
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module->connect(RTLIL::SigSig(sig_y, sig_ab));
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}
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static void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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int width = cell->parameters.at("\\WIDTH").as_int();
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char set_pol = cell->parameters.at("\\SET_POLARITY").as_bool() ? 'P' : 'N';
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char clr_pol = cell->parameters.at("\\CLR_POLARITY").as_bool() ? 'P' : 'N';
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RTLIL::SigSpec sig_s = cell->get("\\SET");
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RTLIL::SigSpec sig_r = cell->get("\\CLR");
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RTLIL::SigSpec sig_q = cell->get("\\Q");
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std::string gate_type = stringf("$_SR_%c%c_", set_pol, clr_pol);
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for (int i = 0; i < width; i++) {
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RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
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gate->set("\\S", sig_s[i]);
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gate->set("\\R", sig_r[i]);
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gate->set("\\Q", sig_q[i]);
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}
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}
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static void simplemap_dff(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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int width = cell->parameters.at("\\WIDTH").as_int();
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char clk_pol = cell->parameters.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N';
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RTLIL::SigSpec sig_clk = cell->get("\\CLK");
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RTLIL::SigSpec sig_d = cell->get("\\D");
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RTLIL::SigSpec sig_q = cell->get("\\Q");
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std::string gate_type = stringf("$_DFF_%c_", clk_pol);
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for (int i = 0; i < width; i++) {
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RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
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gate->set("\\C", sig_clk);
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gate->set("\\D", sig_d[i]);
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gate->set("\\Q", sig_q[i]);
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}
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}
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static void simplemap_dffsr(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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int width = cell->parameters.at("\\WIDTH").as_int();
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char clk_pol = cell->parameters.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N';
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char set_pol = cell->parameters.at("\\SET_POLARITY").as_bool() ? 'P' : 'N';
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char clr_pol = cell->parameters.at("\\CLR_POLARITY").as_bool() ? 'P' : 'N';
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RTLIL::SigSpec sig_clk = cell->get("\\CLK");
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RTLIL::SigSpec sig_s = cell->get("\\SET");
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RTLIL::SigSpec sig_r = cell->get("\\CLR");
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RTLIL::SigSpec sig_d = cell->get("\\D");
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RTLIL::SigSpec sig_q = cell->get("\\Q");
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std::string gate_type = stringf("$_DFFSR_%c%c%c_", clk_pol, set_pol, clr_pol);
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for (int i = 0; i < width; i++) {
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RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
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gate->set("\\C", sig_clk);
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gate->set("\\S", sig_s[i]);
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gate->set("\\R", sig_r[i]);
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gate->set("\\D", sig_d[i]);
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gate->set("\\Q", sig_q[i]);
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}
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}
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static void simplemap_adff(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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int width = cell->parameters.at("\\WIDTH").as_int();
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char clk_pol = cell->parameters.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N';
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char rst_pol = cell->parameters.at("\\ARST_POLARITY").as_bool() ? 'P' : 'N';
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std::vector<RTLIL::State> rst_val = cell->parameters.at("\\ARST_VALUE").bits;
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while (int(rst_val.size()) < width)
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rst_val.push_back(RTLIL::State::S0);
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RTLIL::SigSpec sig_clk = cell->get("\\CLK");
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RTLIL::SigSpec sig_rst = cell->get("\\ARST");
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RTLIL::SigSpec sig_d = cell->get("\\D");
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RTLIL::SigSpec sig_q = cell->get("\\Q");
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std::string gate_type_0 = stringf("$_DFF_%c%c0_", clk_pol, rst_pol);
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std::string gate_type_1 = stringf("$_DFF_%c%c1_", clk_pol, rst_pol);
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for (int i = 0; i < width; i++) {
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RTLIL::Cell *gate = module->addCell(NEW_ID, rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0);
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gate->set("\\C", sig_clk);
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gate->set("\\R", sig_rst);
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gate->set("\\D", sig_d[i]);
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gate->set("\\Q", sig_q[i]);
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}
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}
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static void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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int width = cell->parameters.at("\\WIDTH").as_int();
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char en_pol = cell->parameters.at("\\EN_POLARITY").as_bool() ? 'P' : 'N';
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RTLIL::SigSpec sig_en = cell->get("\\EN");
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RTLIL::SigSpec sig_d = cell->get("\\D");
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RTLIL::SigSpec sig_q = cell->get("\\Q");
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std::string gate_type = stringf("$_DLATCH_%c_", en_pol);
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for (int i = 0; i < width; i++) {
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RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
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gate->set("\\E", sig_en);
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gate->set("\\D", sig_d[i]);
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gate->set("\\Q", sig_q[i]);
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}
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}
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void simplemap_get_mappers(std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers)
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{
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mappers["$not"] = simplemap_not;
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mappers["$pos"] = simplemap_pos;
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mappers["$bu0"] = simplemap_bu0;
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mappers["$and"] = simplemap_bitop;
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mappers["$or"] = simplemap_bitop;
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mappers["$xor"] = simplemap_bitop;
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mappers["$xnor"] = simplemap_bitop;
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mappers["$reduce_and"] = simplemap_reduce;
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mappers["$reduce_or"] = simplemap_reduce;
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mappers["$reduce_xor"] = simplemap_reduce;
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mappers["$reduce_xnor"] = simplemap_reduce;
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mappers["$reduce_bool"] = simplemap_reduce;
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mappers["$logic_not"] = simplemap_lognot;
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mappers["$logic_and"] = simplemap_logbin;
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mappers["$logic_or"] = simplemap_logbin;
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mappers["$mux"] = simplemap_mux;
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mappers["$slice"] = simplemap_slice;
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mappers["$concat"] = simplemap_concat;
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mappers["$sr"] = simplemap_sr;
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mappers["$dff"] = simplemap_dff;
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mappers["$dffsr"] = simplemap_dffsr;
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mappers["$adff"] = simplemap_adff;
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mappers["$dlatch"] = simplemap_dlatch;
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}
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struct SimplemapPass : public Pass {
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SimplemapPass() : Pass("simplemap", "mapping simple coarse-grain cells") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" simplemap [selection]\n");
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log("\n");
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log("This pass maps a small selection of simple coarse-grain cells to yosys gate\n");
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log("primitives. The following internal cell types are mapped by this pass:\n");
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log("\n");
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log(" $not, $pos, $bu0, $and, $or, $xor, $xnor\n");
|
|
log(" $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool\n");
|
|
log(" $logic_not, $logic_and, $logic_or, $mux\n");
|
|
log(" $sr, $dff, $dffsr, $adff, $dlatch\n");
|
|
log("\n");
|
|
}
|
|
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
|
|
{
|
|
log_header("Executing SIMPLEMAP pass (map simple cells to gate primitives).\n");
|
|
extra_args(args, 1, design);
|
|
|
|
std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> mappers;
|
|
simplemap_get_mappers(mappers);
|
|
|
|
for (auto mod : design->modules()) {
|
|
if (!design->selected(mod))
|
|
continue;
|
|
std::vector<RTLIL::Cell*> cells = mod->cells();
|
|
for (auto cell : cells) {
|
|
if (mappers.count(cell->type) == 0)
|
|
continue;
|
|
if (!design->selected(mod, cell))
|
|
continue;
|
|
log("Mapping %s.%s (%s).\n", log_id(mod), log_id(cell), log_id(cell->type));
|
|
mappers.at(cell->type)(mod, cell);
|
|
mod->remove(cell);
|
|
}
|
|
}
|
|
}
|
|
} SimplemapPass;
|
|
|