mirror of https://github.com/YosysHQ/yosys.git
777 lines
26 KiB
C++
777 lines
26 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/log.h"
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#include <string.h>
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#include <dirent.h>
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#include <readline/readline.h>
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using RTLIL::id2cstr;
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#undef CLUSTER_CELLS_AND_PORTBOXES
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struct ShowWorker
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{
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CellTypes ct;
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std::vector<std::string> dot_escape_store;
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std::map<RTLIL::IdString, int> dot_id2num_store;
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std::map<RTLIL::IdString, int> autonames;
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int single_idx_count;
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struct net_conn { std::set<std::string> in, out; int bits; std::string color; };
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std::map<std::string, net_conn> net_conn_map;
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FILE *f;
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RTLIL::Design *design;
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RTLIL::Module *module;
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uint32_t currentColor;
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bool genWidthLabels;
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bool stretchIO;
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bool enumerateIds;
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bool abbreviateIds;
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bool notitle;
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int page_counter;
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const std::vector<std::pair<std::string, RTLIL::Selection>> &color_selections;
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const std::vector<std::pair<std::string, RTLIL::Selection>> &label_selections;
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static uint32_t xorshift32(uint32_t x) {
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x ^= x << 13;
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x ^= x >> 17;
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x ^= x << 5;
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return x;
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}
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std::string nextColor()
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{
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if (currentColor == 0)
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return "color=\"black\"";
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return stringf("colorscheme=\"dark28\", color=\"%d\", fontcolor=\"%d\"", currentColor%8+1);
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}
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std::string nextColor(std::string presetColor)
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{
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if (presetColor.empty())
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return nextColor();
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return presetColor;
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}
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std::string nextColor(RTLIL::SigSpec sig, std::string defaultColor)
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{
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sig.sort_and_unify();
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for (auto &c : sig.chunks()) {
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if (c.wire != NULL)
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for (auto &s : color_selections)
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if (s.second.selected_members.count(module->name) > 0 && s.second.selected_members.at(module->name).count(c.wire->name) > 0)
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return stringf("color=\"%s\"", s.first.c_str());
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}
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return defaultColor;
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}
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std::string nextColor(const RTLIL::SigSig &conn, std::string defaultColor)
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{
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return nextColor(conn.first, nextColor(conn.second, defaultColor));
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}
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std::string nextColor(const RTLIL::SigSpec &sig)
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{
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return nextColor(sig, nextColor());
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}
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std::string nextColor(const RTLIL::SigSig &conn)
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{
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return nextColor(conn, nextColor());
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}
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std::string widthLabel(int bits)
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{
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if (bits <= 1)
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return "label=\"\"";
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if (!genWidthLabels)
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return "style=\"setlinewidth(3)\", label=\"\"";
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return stringf("style=\"setlinewidth(3)\", label=\"<%d>\"", bits);
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}
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const char *findColor(std::string member_name)
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{
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for (auto &s : color_selections)
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if (s.second.selected_member(module->name, member_name)) {
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dot_escape_store.push_back(stringf(", color=\"%s\"", s.first.c_str()));
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return dot_escape_store.back().c_str();
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}
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return "";
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}
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const char *findLabel(std::string member_name)
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{
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for (auto &s : label_selections)
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if (s.second.selected_member(module->name, RTLIL::escape_id(member_name)))
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return escape(s.first);
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return escape(member_name, true);
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}
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const char *escape(std::string id, bool is_name = false)
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{
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if (id.size() == 0)
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return "";
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if (id[0] == '$' && is_name) {
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if (enumerateIds) {
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if (autonames.count(id) == 0) {
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autonames[id] = autonames.size() + 1;
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log("Generated short name for internal identifier: _%d_ -> %s\n", autonames[id], id.c_str());
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}
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id = stringf("_%d_", autonames[id]);
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} else if (abbreviateIds) {
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const char *p = id.c_str();
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const char *q = strrchr(p, '$');
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id = std::string(q);
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}
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}
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if (id[0] == '\\')
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id = id.substr(1);
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std::string str;
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for (char ch : id) {
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if (ch == '\\' || ch == '"')
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str += "\\";
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str += ch;
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}
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dot_escape_store.push_back(str);
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return dot_escape_store.back().c_str();
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}
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int id2num(RTLIL::IdString id)
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{
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if (dot_id2num_store.count(id) > 0)
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return dot_id2num_store[id];
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return dot_id2num_store[id] = dot_id2num_store.size() + 1;
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}
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std::string gen_signode_simple(RTLIL::SigSpec sig, bool range_check = true)
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{
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if (SIZE(sig) == 0) {
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fprintf(f, "v%d [ label=\"\" ];\n", single_idx_count);
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return stringf("v%d", single_idx_count++);
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}
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if (sig.is_chunk()) {
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const RTLIL::SigChunk &c = sig.as_chunk();
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if (c.wire != NULL && design->selected_member(module->name, c.wire->name)) {
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if (!range_check || c.wire->width == c.width)
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return stringf("n%d", id2num(c.wire->name));
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} else {
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fprintf(f, "v%d [ label=\"%s\" ];\n", single_idx_count, findLabel(log_signal(c)));
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return stringf("v%d", single_idx_count++);
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}
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}
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return std::string();
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}
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std::string gen_portbox(std::string port, RTLIL::SigSpec sig, bool driver, std::string *node = NULL)
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{
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std::string code;
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std::string net = gen_signode_simple(sig);
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if (net.empty())
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{
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std::string label_string;
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int pos = sig.size()-1;
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int idx = single_idx_count++;
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for (int i = int(sig.chunks().size())-1; i >= 0; i--) {
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const RTLIL::SigChunk &c = sig.chunks().at(i);
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net = gen_signode_simple(c, false);
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assert(!net.empty());
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if (driver) {
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label_string += stringf("<s%d> %d:%d - %d:%d |", i, pos, pos-c.width+1, c.offset+c.width-1, c.offset);
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net_conn_map[net].in.insert(stringf("x%d:s%d", idx, i));
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net_conn_map[net].bits = c.width;
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net_conn_map[net].color = nextColor(c, net_conn_map[net].color);
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} else {
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label_string += stringf("<s%d> %d:%d - %d:%d |", i, c.offset+c.width-1, c.offset, pos, pos-c.width+1);
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net_conn_map[net].out.insert(stringf("x%d:s%d", idx, i));
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net_conn_map[net].bits = c.width;
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net_conn_map[net].color = nextColor(c, net_conn_map[net].color);
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}
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pos -= c.width;
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}
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if (label_string[label_string.size()-1] == '|')
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label_string = label_string.substr(0, label_string.size()-1);
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code += stringf("x%d [ shape=record, style=rounded, label=\"%s\" ];\n", idx, label_string.c_str());
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if (!port.empty()) {
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currentColor = xorshift32(currentColor);
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if (driver)
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code += stringf("%s:e -> x%d:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", port.c_str(), idx, nextColor(sig).c_str(), widthLabel(sig.size()).c_str());
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else
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code += stringf("x%d:e -> %s:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", idx, port.c_str(), nextColor(sig).c_str(), widthLabel(sig.size()).c_str());
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}
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if (node != NULL)
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*node = stringf("x%d", idx);
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}
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else
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{
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if (!port.empty()) {
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if (driver)
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net_conn_map[net].in.insert(port);
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else
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net_conn_map[net].out.insert(port);
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net_conn_map[net].bits = sig.size();
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net_conn_map[net].color = nextColor(sig, net_conn_map[net].color);
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}
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if (node != NULL)
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*node = net;
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}
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return code;
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}
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void collect_proc_signals(std::vector<RTLIL::SigSpec> &obj, std::set<RTLIL::SigSpec> &signals)
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{
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for (auto &it : obj)
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if (!it.is_fully_const())
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signals.insert(it);
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}
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void collect_proc_signals(std::vector<RTLIL::SigSig> &obj, std::set<RTLIL::SigSpec> &input_signals, std::set<RTLIL::SigSpec> &output_signals)
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{
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for (auto &it : obj) {
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output_signals.insert(it.first);
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if (!it.second.is_fully_const())
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input_signals.insert(it.second);
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}
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}
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void collect_proc_signals(RTLIL::CaseRule *obj, std::set<RTLIL::SigSpec> &input_signals, std::set<RTLIL::SigSpec> &output_signals)
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{
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collect_proc_signals(obj->compare, input_signals);
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collect_proc_signals(obj->actions, input_signals, output_signals);
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for (auto it : obj->switches)
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collect_proc_signals(it, input_signals, output_signals);
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}
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void collect_proc_signals(RTLIL::SwitchRule *obj, std::set<RTLIL::SigSpec> &input_signals, std::set<RTLIL::SigSpec> &output_signals)
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{
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input_signals.insert(obj->signal);
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for (auto it : obj->cases)
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collect_proc_signals(it, input_signals, output_signals);
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}
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void collect_proc_signals(RTLIL::SyncRule *obj, std::set<RTLIL::SigSpec> &input_signals, std::set<RTLIL::SigSpec> &output_signals)
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{
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input_signals.insert(obj->signal);
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collect_proc_signals(obj->actions, input_signals, output_signals);
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}
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void collect_proc_signals(RTLIL::Process *obj, std::set<RTLIL::SigSpec> &input_signals, std::set<RTLIL::SigSpec> &output_signals)
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{
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collect_proc_signals(&obj->root_case, input_signals, output_signals);
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for (auto it : obj->syncs)
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collect_proc_signals(it, input_signals, output_signals);
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}
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void handle_module()
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{
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single_idx_count = 0;
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dot_escape_store.clear();
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dot_id2num_store.clear();
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net_conn_map.clear();
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fprintf(f, "digraph \"%s\" {\n", escape(module->name));
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if (!notitle)
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fprintf(f, "label=\"%s\";\n", escape(module->name));
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fprintf(f, "rankdir=\"LR\";\n");
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fprintf(f, "remincross=true;\n");
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std::set<std::string> all_sources, all_sinks;
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std::map<std::string, std::string> wires_on_demand;
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for (auto &it : module->wires_) {
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if (!design->selected_member(module->name, it.first))
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continue;
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const char *shape = "diamond";
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if (it.second->port_input || it.second->port_output)
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shape = "octagon";
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if (it.first[0] == '\\') {
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fprintf(f, "n%d [ shape=%s, label=\"%s\", %s, fontcolor=\"black\" ];\n",
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id2num(it.first), shape, findLabel(it.first),
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nextColor(RTLIL::SigSpec(it.second), "color=\"black\"").c_str());
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if (it.second->port_input)
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all_sources.insert(stringf("n%d", id2num(it.first)));
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else if (it.second->port_output)
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all_sinks.insert(stringf("n%d", id2num(it.first)));
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} else {
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wires_on_demand[stringf("n%d", id2num(it.first))] = it.first;
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}
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}
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if (stretchIO)
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{
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fprintf(f, "{ rank=\"source\";");
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for (auto n : all_sources)
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fprintf(f, " %s;", n.c_str());
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fprintf(f, "}\n");
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fprintf(f, "{ rank=\"sink\";");
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for (auto n : all_sinks)
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fprintf(f, " %s;", n.c_str());
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fprintf(f, "}\n");
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}
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for (auto &it : module->cells_)
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{
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if (!design->selected_member(module->name, it.first))
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continue;
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std::vector<RTLIL::IdString> in_ports, out_ports;
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for (auto &conn : it.second->connections()) {
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if (!ct.cell_output(it.second->type, conn.first))
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in_ports.push_back(conn.first);
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else
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out_ports.push_back(conn.first);
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}
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std::string label_string = "{{";
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for (auto &p : in_ports)
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label_string += stringf("<p%d> %s|", id2num(p), escape(p));
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if (label_string[label_string.size()-1] == '|')
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label_string = label_string.substr(0, label_string.size()-1);
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label_string += stringf("}|%s\\n%s|{", findLabel(it.first), escape(it.second->type));
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for (auto &p : out_ports)
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label_string += stringf("<p%d> %s|", id2num(p), escape(p));
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if (label_string[label_string.size()-1] == '|')
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label_string = label_string.substr(0, label_string.size()-1);
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label_string += "}}";
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std::string code;
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for (auto &conn : it.second->connections()) {
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code += gen_portbox(stringf("c%d:p%d", id2num(it.first), id2num(conn.first)),
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conn.second, ct.cell_output(it.second->type, conn.first));
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}
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#ifdef CLUSTER_CELLS_AND_PORTBOXES
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if (!code.empty())
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fprintf(f, "subgraph cluster_c%d {\nc%d [ shape=record, label=\"%s\"%s ];\n%s}\n",
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id2num(it.first), id2num(it.first), label_string.c_str(), findColor(it.first), code.c_str());
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else
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#endif
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fprintf(f, "c%d [ shape=record, label=\"%s\"%s ];\n%s",
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id2num(it.first), label_string.c_str(), findColor(it.first), code.c_str());
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}
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for (auto &it : module->processes)
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{
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RTLIL::Process *proc = it.second;
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if (!design->selected_member(module->name, proc->name))
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continue;
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std::set<RTLIL::SigSpec> input_signals, output_signals;
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collect_proc_signals(proc, input_signals, output_signals);
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int pidx = single_idx_count++;
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input_signals.erase(RTLIL::SigSpec());
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output_signals.erase(RTLIL::SigSpec());
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for (auto &sig : input_signals) {
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std::string code, node;
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code += gen_portbox("", sig, false, &node);
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fprintf(f, "%s", code.c_str());
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net_conn_map[node].out.insert(stringf("p%d", pidx));
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net_conn_map[node].bits = sig.size();
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net_conn_map[node].color = nextColor(sig, net_conn_map[node].color);
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}
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for (auto &sig : output_signals) {
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std::string code, node;
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code += gen_portbox("", sig, true, &node);
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fprintf(f, "%s", code.c_str());
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net_conn_map[node].in.insert(stringf("p%d", pidx));
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net_conn_map[node].bits = sig.size();
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net_conn_map[node].color = nextColor(sig, net_conn_map[node].color);
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}
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std::string proc_src = RTLIL::unescape_id(proc->name);
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if (proc->attributes.count("\\src") > 0)
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proc_src = proc->attributes.at("\\src").decode_string();
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fprintf(f, "p%d [shape=box, style=rounded, label=\"PROC %s\\n%s\"];\n", pidx, findLabel(proc->name), proc_src.c_str());
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}
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for (auto &conn : module->connections())
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{
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bool found_lhs_wire = false;
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for (auto &c : conn.first.chunks()) {
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if (c.wire == NULL || design->selected_member(module->name, c.wire->name))
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found_lhs_wire = true;
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}
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bool found_rhs_wire = false;
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for (auto &c : conn.second.chunks()) {
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if (c.wire == NULL || design->selected_member(module->name, c.wire->name))
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found_rhs_wire = true;
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}
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if (!found_lhs_wire || !found_rhs_wire)
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continue;
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std::string code, left_node, right_node;
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code += gen_portbox("", conn.second, false, &left_node);
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code += gen_portbox("", conn.first, true, &right_node);
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fprintf(f, "%s", code.c_str());
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if (left_node[0] == 'x' && right_node[0] == 'x') {
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currentColor = xorshift32(currentColor);
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fprintf(f, "%s:e -> %s:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", left_node.c_str(), right_node.c_str(), nextColor(conn).c_str(), widthLabel(conn.first.size()).c_str());
|
|
} else {
|
|
net_conn_map[right_node].bits = conn.first.size();
|
|
net_conn_map[right_node].color = nextColor(conn, net_conn_map[right_node].color);
|
|
net_conn_map[left_node].bits = conn.first.size();
|
|
net_conn_map[left_node].color = nextColor(conn, net_conn_map[left_node].color);
|
|
if (left_node[0] == 'x') {
|
|
net_conn_map[right_node].in.insert(left_node);
|
|
} else if (right_node[0] == 'x') {
|
|
net_conn_map[left_node].out.insert(right_node);
|
|
} else {
|
|
net_conn_map[right_node].in.insert(stringf("x%d:e", single_idx_count));
|
|
net_conn_map[left_node].out.insert(stringf("x%d:w", single_idx_count));
|
|
fprintf(f, "x%d [shape=box, style=rounded, label=\"BUF\"];\n", single_idx_count++);
|
|
}
|
|
}
|
|
}
|
|
|
|
for (auto &it : net_conn_map)
|
|
{
|
|
currentColor = xorshift32(currentColor);
|
|
if (wires_on_demand.count(it.first) > 0) {
|
|
if (it.second.in.size() == 1 && it.second.out.size() > 1 && it.second.in.begin()->substr(0, 1) == "p")
|
|
it.second.out.erase(*it.second.in.begin());
|
|
if (it.second.in.size() == 1 && it.second.out.size() == 1) {
|
|
std::string from = *it.second.in.begin(), to = *it.second.out.begin();
|
|
if (from != to || from.substr(0, 1) != "p")
|
|
fprintf(f, "%s:e -> %s:w [%s, %s];\n", from.c_str(), to.c_str(), nextColor(it.second.color).c_str(), widthLabel(it.second.bits).c_str());
|
|
continue;
|
|
}
|
|
if (it.second.in.size() == 0 || it.second.out.size() == 0)
|
|
fprintf(f, "%s [ shape=diamond, label=\"%s\" ];\n", it.first.c_str(), findLabel(wires_on_demand[it.first]));
|
|
else
|
|
fprintf(f, "%s [ shape=point ];\n", it.first.c_str());
|
|
}
|
|
for (auto &it2 : it.second.in)
|
|
fprintf(f, "%s:e -> %s:w [%s, %s];\n", it2.c_str(), it.first.c_str(), nextColor(it.second.color).c_str(), widthLabel(it.second.bits).c_str());
|
|
for (auto &it2 : it.second.out)
|
|
fprintf(f, "%s:e -> %s:w [%s, %s];\n", it.first.c_str(), it2.c_str(), nextColor(it.second.color).c_str(), widthLabel(it.second.bits).c_str());
|
|
}
|
|
|
|
fprintf(f, "}\n");
|
|
}
|
|
|
|
ShowWorker(FILE *f, RTLIL::Design *design, std::vector<RTLIL::Design*> &libs, uint32_t colorSeed,
|
|
bool genWidthLabels, bool stretchIO, bool enumerateIds, bool abbreviateIds, bool notitle,
|
|
const std::vector<std::pair<std::string, RTLIL::Selection>> &color_selections,
|
|
const std::vector<std::pair<std::string, RTLIL::Selection>> &label_selections) :
|
|
f(f), design(design), currentColor(colorSeed), genWidthLabels(genWidthLabels),
|
|
stretchIO(stretchIO), enumerateIds(enumerateIds), abbreviateIds(abbreviateIds),
|
|
notitle(notitle), color_selections(color_selections), label_selections(label_selections)
|
|
{
|
|
ct.setup_internals();
|
|
ct.setup_internals_mem();
|
|
ct.setup_stdcells();
|
|
ct.setup_stdcells_mem();
|
|
ct.setup_design(design);
|
|
|
|
for (auto lib : libs)
|
|
ct.setup_design(lib);
|
|
|
|
design->optimize();
|
|
page_counter = 0;
|
|
for (auto &mod_it : design->modules_)
|
|
{
|
|
module = mod_it.second;
|
|
if (!design->selected_module(module->name))
|
|
continue;
|
|
if (design->selected_whole_module(module->name)) {
|
|
if (module->get_bool_attribute("\\blackbox")) {
|
|
log("Skipping blackbox module %s.\n", id2cstr(module->name));
|
|
continue;
|
|
} else
|
|
if (module->cells_.empty() && module->connections().empty() && module->processes.empty()) {
|
|
log("Skipping empty module %s.\n", id2cstr(module->name));
|
|
continue;
|
|
} else
|
|
log("Dumping module %s to page %d.\n", id2cstr(module->name), ++page_counter);
|
|
} else
|
|
log("Dumping selected parts of module %s to page %d.\n", id2cstr(module->name), ++page_counter);
|
|
handle_module();
|
|
}
|
|
}
|
|
};
|
|
|
|
struct ShowPass : public Pass {
|
|
ShowPass() : Pass("show", "generate schematics using graphviz") { }
|
|
virtual void help()
|
|
{
|
|
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
|
log("\n");
|
|
log(" show [options] [selection]\n");
|
|
log("\n");
|
|
log("Create a graphviz DOT file for the selected part of the design and compile it\n");
|
|
log("to a graphics file (usually SVG or PostScript).\n");
|
|
log("\n");
|
|
log(" -viewer <viewer>\n");
|
|
log(" Run the specified command with the graphics file as parameter.\n");
|
|
log("\n");
|
|
log(" -format <format>\n");
|
|
log(" Generate a graphics file in the specified format.\n");
|
|
log(" Usually <format> is 'svg' or 'ps'.\n");
|
|
log("\n");
|
|
log(" -lib <verilog_or_ilang_file>\n");
|
|
log(" Use the specified library file for determining whether cell ports are\n");
|
|
log(" inputs or outputs. This option can be used multiple times to specify\n");
|
|
log(" more than one library.\n");
|
|
log("\n");
|
|
log(" -prefix <prefix>\n");
|
|
log(" generate <prefix>.* instead of ~/.yosys_show.*\n");
|
|
log("\n");
|
|
log(" -color <color> <object>\n");
|
|
log(" assign the specified color to the specified object. The object can be\n");
|
|
log(" a single selection wildcard expressions or a saved set of objects in\n");
|
|
log(" the @<name> syntax (see \"help select\" for details).\n");
|
|
log("\n");
|
|
log(" -label <text> <object>\n");
|
|
log(" assign the specified label text to the specified object. The object can\n");
|
|
log(" be a single selection wildcard expressions or a saved set of objects in\n");
|
|
log(" the @<name> syntax (see \"help select\" for details).\n");
|
|
log("\n");
|
|
log(" -colors <seed>\n");
|
|
log(" Randomly assign colors to the wires. The integer argument is the seed\n");
|
|
log(" for the random number generator. Change the seed value if the colored\n");
|
|
log(" graph still is ambigous. A seed of zero deactivates the coloring.\n");
|
|
log("\n");
|
|
log(" -width\n");
|
|
log(" annotate busses with a label indicating the width of the bus.\n");
|
|
log("\n");
|
|
log(" -stretch\n");
|
|
log(" stretch the graph so all inputs are on the left side and all outputs\n");
|
|
log(" (including inout ports) are on the right side.\n");
|
|
log("\n");
|
|
log(" -pause\n");
|
|
log(" wait for the use to press enter to before returning\n");
|
|
log("\n");
|
|
log(" -enum\n");
|
|
log(" enumerate objects with internal ($-prefixed) names\n");
|
|
log("\n");
|
|
log(" -long\n");
|
|
log(" do not abbeviate objects with internal ($-prefixed) names\n");
|
|
log("\n");
|
|
log(" -notitle\n");
|
|
log(" do not add the module name as graph title to the dot file\n");
|
|
log("\n");
|
|
log("When no <format> is specified, SVG is used. When no <format> and <viewer> is\n");
|
|
log("specified, 'yosys-svgviewer' is used to display the schematic.\n");
|
|
log("\n");
|
|
log("The generated output files are '~/.yosys_show.dot' and '~/.yosys_show.<format>',\n");
|
|
log("unless another prefix is specified using -prefix <prefix>.\n");
|
|
log("\n");
|
|
}
|
|
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
|
|
{
|
|
log_header("Generating Graphviz representation of design.\n");
|
|
log_push();
|
|
|
|
std::vector<std::pair<std::string, RTLIL::Selection>> color_selections;
|
|
std::vector<std::pair<std::string, RTLIL::Selection>> label_selections;
|
|
|
|
std::string format;
|
|
std::string viewer_exe;
|
|
std::string prefix = stringf("%s/.yosys_show", getenv("HOME") ? getenv("HOME") : ".");
|
|
std::vector<std::string> libfiles;
|
|
std::vector<RTLIL::Design*> libs;
|
|
uint32_t colorSeed = 0;
|
|
bool flag_width = false;
|
|
bool flag_stretch = false;
|
|
bool flag_pause = false;
|
|
bool flag_enum = false;
|
|
bool flag_abbeviate = true;
|
|
bool flag_notitle = false;
|
|
|
|
size_t argidx;
|
|
for (argidx = 1; argidx < args.size(); argidx++)
|
|
{
|
|
std::string arg = args[argidx];
|
|
if (arg == "-viewer" && argidx+1 < args.size()) {
|
|
viewer_exe = args[++argidx];
|
|
continue;
|
|
}
|
|
if (arg == "-lib" && argidx+1 < args.size()) {
|
|
libfiles.push_back(args[++argidx]);
|
|
continue;
|
|
}
|
|
if (arg == "-prefix" && argidx+1 < args.size()) {
|
|
prefix = args[++argidx];
|
|
continue;
|
|
}
|
|
if (arg == "-color" && argidx+2 < args.size()) {
|
|
std::pair<std::string, RTLIL::Selection> data;
|
|
data.first = args[++argidx], argidx++;
|
|
handle_extra_select_args(this, args, argidx, argidx+1, design);
|
|
data.second = design->selection_stack.back();
|
|
design->selection_stack.pop_back();
|
|
color_selections.push_back(data);
|
|
continue;
|
|
}
|
|
if (arg == "-label" && argidx+2 < args.size()) {
|
|
std::pair<std::string, RTLIL::Selection> data;
|
|
data.first = args[++argidx], argidx++;
|
|
handle_extra_select_args(this, args, argidx, argidx+1, design);
|
|
data.second = design->selection_stack.back();
|
|
design->selection_stack.pop_back();
|
|
label_selections.push_back(data);
|
|
continue;
|
|
}
|
|
if (arg == "-colors" && argidx+1 < args.size()) {
|
|
colorSeed = atoi(args[++argidx].c_str());
|
|
for (int i = 0; i < 100; i++)
|
|
colorSeed = ShowWorker::xorshift32(colorSeed);
|
|
continue;
|
|
}
|
|
if (arg == "-format" && argidx+1 < args.size()) {
|
|
format = args[++argidx];
|
|
continue;
|
|
}
|
|
if (arg == "-width") {
|
|
flag_width= true;
|
|
continue;
|
|
}
|
|
if (arg == "-stretch") {
|
|
flag_stretch= true;
|
|
continue;
|
|
}
|
|
if (arg == "-pause") {
|
|
flag_pause= true;
|
|
continue;
|
|
}
|
|
if (arg == "-enum") {
|
|
flag_enum = true;
|
|
flag_abbeviate = false;
|
|
continue;
|
|
}
|
|
if (arg == "-long") {
|
|
flag_enum = false;
|
|
flag_abbeviate = false;
|
|
continue;
|
|
}
|
|
if (arg == "-notitle") {
|
|
flag_notitle = true;
|
|
continue;
|
|
}
|
|
break;
|
|
}
|
|
extra_args(args, argidx, design);
|
|
|
|
if (format != "ps") {
|
|
int modcount = 0;
|
|
for (auto &mod_it : design->modules_) {
|
|
if (mod_it.second->get_bool_attribute("\\blackbox"))
|
|
continue;
|
|
if (mod_it.second->cells_.empty() && mod_it.second->connections().empty())
|
|
continue;
|
|
if (design->selected_module(mod_it.first))
|
|
modcount++;
|
|
}
|
|
if (modcount > 1)
|
|
log_cmd_error("For formats different than 'ps' only one module must be selected.\n");
|
|
}
|
|
|
|
for (auto filename : libfiles) {
|
|
FILE *f = fopen(filename.c_str(), "rt");
|
|
if (f == NULL)
|
|
log_error("Can't open lib file `%s'.\n", filename.c_str());
|
|
RTLIL::Design *lib = new RTLIL::Design;
|
|
Frontend::frontend_call(lib, f, filename, (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") ? "ilang" : "verilog");
|
|
libs.push_back(lib);
|
|
fclose(f);
|
|
}
|
|
|
|
if (libs.size() > 0)
|
|
log_header("Continuing show pass.\n");
|
|
|
|
std::string dot_file = stringf("%s.dot", prefix.c_str());
|
|
std::string out_file = stringf("%s.%s", prefix.c_str(), format.empty() ? "svg" : format.c_str());
|
|
|
|
log("Writing dot description to `%s'.\n", dot_file.c_str());
|
|
FILE *f = fopen(dot_file.c_str(), "w");
|
|
if (f == NULL) {
|
|
for (auto lib : libs)
|
|
delete lib;
|
|
log_cmd_error("Can't open dot file `%s' for writing.\n", dot_file.c_str());
|
|
}
|
|
ShowWorker worker(f, design, libs, colorSeed, flag_width, flag_stretch, flag_enum, flag_abbeviate, flag_notitle, color_selections, label_selections);
|
|
fclose(f);
|
|
|
|
for (auto lib : libs)
|
|
delete lib;
|
|
|
|
if (worker.page_counter == 0)
|
|
log_cmd_error("Nothing there to show.\n");
|
|
|
|
if (format != "dot") {
|
|
std::string cmd = stringf("dot -T%s -o '%s' '%s'", format.empty() ? "svg" : format.c_str(), out_file.c_str(), dot_file.c_str());
|
|
log("Exec: %s\n", cmd.c_str());
|
|
if (system(cmd.c_str()) != 0)
|
|
log_cmd_error("Shell command failed!\n");
|
|
}
|
|
|
|
if (!viewer_exe.empty()) {
|
|
std::string cmd = stringf("%s '%s' &", viewer_exe.c_str(), out_file.c_str());
|
|
log("Exec: %s\n", cmd.c_str());
|
|
if (system(cmd.c_str()) != 0)
|
|
log_cmd_error("Shell command failed!\n");
|
|
} else
|
|
if (format.empty()) {
|
|
std::string svgviewer = proc_self_dirname() + "yosys-svgviewer";
|
|
std::string cmd = stringf("fuser -s '%s' || '%s' '%s' &", out_file.c_str(), svgviewer.c_str(), out_file.c_str());
|
|
log("Exec: %s\n", cmd.c_str());
|
|
if (system(cmd.c_str()) != 0)
|
|
log_cmd_error("Shell command failed!\n");
|
|
}
|
|
|
|
if (flag_pause) {
|
|
char *input = NULL;
|
|
while ((input = readline("Press ENTER to continue (or type 'shell' to open a shell)> ")) != NULL) {
|
|
if (input[strspn(input, " \t\r\n")] == 0)
|
|
break;
|
|
char *p = input + strspn(input, " \t\r\n");
|
|
if (!strcmp(p, "shell")) {
|
|
Pass::call(design, "shell");
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
log_pop();
|
|
}
|
|
} ShowPass;
|
|
|