mirror of https://github.com/YosysHQ/yosys.git
64 lines
2.2 KiB
C++
64 lines
2.2 KiB
C++
/* -*- c++ -*-
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef CELLEDGES_H
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#define CELLEDGES_H
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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YOSYS_NAMESPACE_BEGIN
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struct AbstractCellEdgesDatabase
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{
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virtual ~AbstractCellEdgesDatabase() { }
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virtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int delay) = 0;
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bool add_edges_from_cell(RTLIL::Cell *cell);
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};
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struct FwdCellEdgesDatabase : AbstractCellEdgesDatabase
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{
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SigMap &sigmap;
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dict<SigBit, pool<SigBit>> db;
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FwdCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { }
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void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) override {
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SigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]);
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SigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]);
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db[from_sigbit].insert(to_sigbit);
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}
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};
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struct RevCellEdgesDatabase : AbstractCellEdgesDatabase
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{
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SigMap &sigmap;
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dict<SigBit, pool<SigBit>> db;
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RevCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { }
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void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) override {
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SigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]);
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SigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]);
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db[to_sigbit].insert(from_sigbit);
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}
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};
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YOSYS_NAMESPACE_END
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#endif
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