yosys/frontends/verilog
Clifford Wolf f050c40519 Various fixes for correct parameter support 2013-11-07 10:02:11 +01:00
..
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00
Makefile.inc initial import 2013-01-05 11:13:26 +01:00
const2ast.cc Major redesign of expr width/sign detecion (verilog/ast frontend) 2013-07-09 14:31:57 +02:00
lexer.l fixed Verilog parser filename and line numbering issue with include files 2013-08-21 09:20:59 +02:00
parser.y Various fixes for correct parameter support 2013-11-07 10:02:11 +01:00
preproc.cc Added support for include directories with the new '-I' argument of the 2013-08-20 15:48:16 +02:00
verilog_frontend.cc Added support for include directories with the new '-I' argument of the 2013-08-20 15:48:16 +02:00
verilog_frontend.h Added support for include directories with the new '-I' argument of the 2013-08-20 15:48:16 +02:00