Clifford Wolf f6629b9c29 Optimize memory address port width in wreduce and memory_collect, not verilog front-end		2016-08-19 18:38:25 +02:00
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ast	Optimize memory address port width in wreduce and memory_collect, not verilog front-end	2016-08-19 18:38:25 +02:00
blif	Added "read_blif -sop"	2016-06-18 12:33:13 +02:00
ilang	Added "yosys -D" feature	2016-04-21 23:28:37 +02:00
liberty	Added "yosys -D" feature	2016-04-21 23:28:37 +02:00
verific	Added "yosys -D" feature	2016-04-21 23:28:37 +02:00
verilog	Fixed bug in parsing real constants	2016-08-06 13:16:23 +02:00
vhdl2verilog	Added "yosys -D" feature	2016-04-21 23:28:37 +02:00