mirror of https://github.com/YosysHQ/yosys.git
20 lines
569 B
Plaintext
20 lines
569 B
Plaintext
read_verilog ../common/lutram.v
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hierarchy -top lutram_1w1r
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proc
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memory -nomap
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equiv_opt -run :prove -map +/nexus/cells_sim.v synth_nexus
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memory
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opt -full
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
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design -load postopt
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cd lutram_1w1r
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stat
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select -assert-count 8 t:WIDEFN9
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select -assert-count 12 t:LUT4
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select -assert-count 8 t:DPR16X4
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select -assert-count 8 t:FD1P3IX
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select -assert-none t:DPR16X4 t:FD1P3IX t:WIDEFN9 t:LUT4 t:INV t:IB t:OB t:VLO t:VHI %% t:* %D
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