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cmds
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Improve "portlist" command
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2019-09-25 09:20:38 +02:00 |
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equiv
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Add equiv_opt -multiclock
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2019-09-11 13:55:59 +01:00 |
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fsm
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RTLIL::S{0,1} -> State::S{0,1}
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2019-08-07 11:12:38 -07:00 |
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hierarchy
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Adopt @cliffordwolf's suggestion
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2019-09-03 12:18:50 -07:00 |
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memory
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stoi -> atoi
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2019-08-07 11:09:17 -07:00 |
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opt
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Revert "SigSet<Cell*> to use stable compare class"
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2019-09-13 09:49:15 -07:00 |
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pmgen
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Ooops AREG and BREG to default to -1
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2019-09-27 11:57:53 -07:00 |
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proc
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proc_clean: fix order of switch insertion.
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2019-08-19 16:44:23 +00:00 |
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sat
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Revert "SigSet<Cell*> to use stable compare class"
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2019-09-13 09:49:15 -07:00 |
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techmap
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Merge pull request #1359 from YosysHQ/xc7dsp
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2019-09-29 11:26:22 -07:00 |
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tests
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Document (* gentb_skip *) attr for test_autotb
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2019-09-18 12:41:35 -07:00 |
8474c5b366