mirror of https://github.com/YosysHQ/yosys.git
20 lines
505 B
Verilog
20 lines
505 B
Verilog
module forloop_select #(parameter WIDTH=16, SELW=4, CTRLW=$clog2(WIDTH), DINW=2**SELW)
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(input clk,
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input [CTRLW-1:0] ctrl,
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input [DINW-1:0] din,
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input en,
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output reg [WIDTH-1:0] dout);
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reg [SELW:0] sel;
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localparam SLICE = WIDTH/(SELW**2);
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always @(posedge clk)
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begin
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if (en) begin
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for (sel = 0; sel <= 4'hf; sel=sel+1'b1)
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dout[(ctrl*sel)+:SLICE] <= din;
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end
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end
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endmodule
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