mirror of https://github.com/YosysHQ/yosys.git
24 lines
648 B
Systemverilog
24 lines
648 B
Systemverilog
function [409600-1:0] bram_init_to_string;
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input [49152-1:0] array;
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input integer blocks;
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input integer width;
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reg [409600-1:0] temp; // (49152+2048)*8 48K bit data + 2k commas
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reg [24-1:0] temp2;
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integer i;
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integer j;
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begin
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temp = "";
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for (i = 0; i < 2048; i = i + 1) begin
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if (i != 0) begin
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temp = {temp, ","};
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end
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temp2 = 24'b0;
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for (j = 0; j < blocks; j = j + 1) begin
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temp2[j*width +: width] = array[{j, i[10:0]}*width +: width];
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end
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temp = {temp, $sformatf("%b",temp2[23:0])};
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end
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bram_init_to_string = temp;
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end
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endfunction
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