mirror of https://github.com/YosysHQ/yosys.git
290 lines
7.8 KiB
C++
290 lines
7.8 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2020 William D. Jones <wjones@wdj-consulting.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct SynthMachXO2Pass : public ScriptPass
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{
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SynthMachXO2Pass() : ScriptPass("synth_machxo2", "synthesis for MachXO2 FPGAs. This work is experimental.") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" synth_machxo2 [options]\n");
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log("\n");
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log("This command runs synthesis for MachXO2 FPGAs.\n");
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log("\n");
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log(" -top <module>\n");
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log(" use the specified module as top module\n");
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log("\n");
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log(" -blif <file>\n");
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log(" write the design to the specified BLIF file. writing of an output file\n");
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log(" is omitted if this parameter is not specified.\n");
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log("\n");
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log(" -edif <file>\n");
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log(" write the design to the specified EDIF file. writing of an output file\n");
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log(" is omitted if this parameter is not specified.\n");
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log("\n");
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log(" -json <file>\n");
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log(" write the design to the specified JSON file. writing of an output file\n");
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log(" is omitted if this parameter is not specified.\n");
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log("\n");
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log(" -run <from_label>:<to_label>\n");
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log(" only run the commands between the labels (see below). an empty\n");
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log(" from label is synonymous to 'begin', and empty to label is\n");
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log(" synonymous to the end of the command list.\n");
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log("\n");
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log(" -nobram\n");
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log(" do not use block RAM cells in output netlist\n");
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log("\n");
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log(" -nolutram\n");
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log(" do not use LUT RAM cells in output netlist\n");
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log("\n");
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log(" -noflatten\n");
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log(" do not flatten design before synthesis\n");
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log("\n");
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log(" -noiopad\n");
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log(" do not insert IO buffers\n");
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log("\n");
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log(" -ccu2\n");
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log(" use CCU2 cells in output netlist\n");
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log("\n");
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log(" -vpr\n");
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log(" generate an output netlist (and BLIF file) suitable for VPR\n");
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log(" (this feature is experimental and incomplete)\n");
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log("\n");
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log("\n");
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log("The following commands are executed by this synthesis command:\n");
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help_script();
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log("\n");
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}
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string top_opt, blif_file, edif_file, json_file;
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bool ccu2, nobram, nolutram, flatten, vpr, noiopad;
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void clear_flags() override
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{
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top_opt = "-auto-top";
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blif_file = "";
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edif_file = "";
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json_file = "";
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ccu2 = false;
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nobram = false;
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nolutram = false;
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flatten = true;
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vpr = false;
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noiopad = false;
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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string run_from, run_to;
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clear_flags();
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-top" && argidx+1 < args.size()) {
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top_opt = "-top " + args[++argidx];
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continue;
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}
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if (args[argidx] == "-blif" && argidx+1 < args.size()) {
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blif_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-edif" && argidx+1 < args.size()) {
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edif_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-json" && argidx+1 < args.size()) {
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json_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-run" && argidx+1 < args.size()) {
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size_t pos = args[argidx+1].find(':');
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if (pos == std::string::npos)
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break;
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run_from = args[++argidx].substr(0, pos);
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run_to = args[argidx].substr(pos+1);
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continue;
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}
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if (args[argidx] == "-flatten") {
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flatten = true;
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continue;
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}
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if (args[argidx] == "-noflatten") {
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flatten = false;
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continue;
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}
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if (args[argidx] == "-nobram") {
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nobram = true;
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continue;
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}
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if (args[argidx] == "-nolutram") {
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nolutram = true;
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continue;
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}
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if (args[argidx] == "-noiopad") {
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noiopad = true;
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continue;
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}
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if (args[argidx] == "-ccu2") {
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ccu2 = true;
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continue;
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}
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if (args[argidx] == "-vpr") {
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vpr = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (!design->full_selection())
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log_cmd_error("This command only operates on fully selected designs!\n");
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log_header(design, "Executing SYNTH_MACHXO2 pass.\n");
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log_push();
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run_script(design, run_from, run_to);
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log_pop();
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}
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void script() override
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{
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if (check_label("begin"))
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{
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run("read_verilog -lib -icells +/machxo2/cells_sim.v");
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run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
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}
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if (check_label("flatten", "(unless -noflatten)"))
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{
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if (flatten || help_mode) {
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run("proc");
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run("flatten");
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run("tribuf -logic");
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run("deminout");
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}
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}
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if (check_label("coarse"))
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{
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run("synth -run coarse");
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}
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if (check_label("map_ram"))
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{
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std::string args = "";
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if (nobram)
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args += " -no-auto-block";
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if (nolutram)
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args += " -no-auto-distributed";
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if (help_mode)
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args += " [-no-auto-block] [-no-auto-distributed]";
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run("memory_libmap -lib +/machxo2/lutrams.txt -lib +/machxo2/brams.txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -nolutram)");
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run("techmap -map +/machxo2/lutrams_map.v -map +/machxo2/brams_map.v");
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}
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if (check_label("fine"))
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{
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run("opt -fast -mux_undef -undriven -fine");
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run("memory_map");
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run("opt -undriven -fine");
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}
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if (check_label("map_gates", "(unless -noiopad)"))
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{
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if (!ccu2)
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run("techmap");
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else
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run("techmap -map +/techmap.v -map +/machxo2/arith_map.v");
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if (!noiopad || help_mode)
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{
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run("iopadmap -bits -outpad OB I:O -inpad IB O:I -toutpad OBZ ~T:I:O -tinoutpad BB ~T:O:I:B A:top", "(only if '-iopad')");
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run("attrmvcp -attr src -attr LOC t:OB %x:+[O] t:OBZ %x:+[O] t:BB %x:+[B]");
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run("attrmvcp -attr src -attr LOC -driven t:IB %x:+[I]");
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}
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}
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if (check_label("map_ffs"))
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{
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run("dfflegalize -cell $_DFF_P_ 0");
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}
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if (check_label("map_luts"))
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{
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run("abc -lut 4 -dress");
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run("clean");
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}
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if (check_label("map_cells"))
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{
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run("techmap -map +/machxo2/cells_map.v");
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run("clean");
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}
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if (check_label("check"))
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{
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run("hierarchy -check");
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run("stat");
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run("blackbox =A:whitebox");
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}
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if (check_label("blif"))
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{
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if (!blif_file.empty() || help_mode) {
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if (vpr || help_mode) {
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run(stringf("opt_clean -purge"),
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" (vpr mode)");
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run(stringf("write_blif -attr -cname -conn -param %s",
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help_mode ? "<file-name>" : blif_file.c_str()),
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" (vpr mode)");
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}
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if (!vpr)
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run(stringf("write_blif -gates -attr -param %s",
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help_mode ? "<file-name>" : blif_file.c_str()),
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" (non-vpr mode)");
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}
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}
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if (check_label("edif"))
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{
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if (!edif_file.empty() || help_mode)
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run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str()));
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}
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if (check_label("json"))
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{
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if (!json_file.empty() || help_mode)
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run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
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}
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}
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} SynthMachXO2Pass;
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PRIVATE_NAMESPACE_END
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