mirror of https://github.com/YosysHQ/yosys.git
13 lines
290 B
Verilog
13 lines
290 B
Verilog
(* abc_box_id = 1 *)
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module SB_CARRY (output CO, input CI, I0, I1);
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assign CO = (I0 && I1) || ((I0 || I1) && CI);
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endmodule
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(* abc_box_id = 2 *)
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module SB_LUT4 (output O, input I0, I1, I2, I3);
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parameter [15:0] LUT_INIT = 0;
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// Indicate this is a black-box
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assign O = 1'b0;
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endmodule
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