yosys/passes/cmds
Clifford Wolf 7f734ecc09 Added module->uniquify() 2014-08-16 23:50:36 +02:00
..
Makefile.inc Added "wreduce" command (work in progress) 2014-08-03 15:02:05 +02:00
add.cc Renamed port access function on RTLIL::Cell, added param access functions 2014-07-31 16:38:54 +02:00
connect.cc Renamed port access function on RTLIL::Cell, added param access functions 2014-07-31 16:38:54 +02:00
connwrappers.cc More cleanups related to RTLIL::IdString usage 2014-08-02 13:19:57 +02:00
copy.cc Added module->design and cell->module, wire->module pointers 2014-07-31 14:11:39 +02:00
cover.cc Disabled cover() for non-linux builds 2014-07-25 12:27:36 +02:00
delete.cc Preparations for RTLIL::IdString redesign: cleanup of existing code 2014-08-02 00:45:25 +02:00
design.cc No implicit conversion from IdString to anything else 2014-08-02 18:58:40 +02:00
log.cc Build fixes for log cmd 2014-02-08 21:21:51 +01:00
rename.cc Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
scatter.cc Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
scc.cc Using log_assert() instead of assert() 2014-07-28 11:27:48 +02:00
select.cc No implicit conversion from IdString to anything else 2014-08-02 18:58:40 +02:00
setattr.cc Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
setundef.cc Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
show.cc Added "show -signed" 2014-08-04 15:40:08 +02:00
splice.cc More cleanups related to RTLIL::IdString usage 2014-08-02 13:19:57 +02:00
splitnets.cc Added module->uniquify() 2014-08-16 23:50:36 +02:00
stat.cc Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
tee.cc Added "trace" command 2014-07-31 15:02:16 +02:00
trace.cc Fixed build with gcc-4.6 2014-08-07 22:37:01 +02:00
wreduce.cc RIP $safe_pmux 2014-08-14 11:39:46 +02:00
write_file.cc Added write_file command 2014-07-30 19:59:29 +02:00