mirror of https://github.com/YosysHQ/yosys.git
312 lines
7.8 KiB
Verilog
312 lines
7.8 KiB
Verilog
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module \$__ICE40_RAM4K (
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output [15:0] RDATA,
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input RCLK, RCLKE, RE,
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input [10:0] RADDR,
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input WCLK, WCLKE, WE,
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input [10:0] WADDR,
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input [15:0] MASK, WDATA
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);
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parameter [1:0] READ_MODE = 0;
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parameter [1:0] WRITE_MODE = 0;
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parameter [0:0] NEGCLK_R = 0;
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parameter [0:0] NEGCLK_W = 0;
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parameter [255:0] INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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generate
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case ({NEGCLK_R, NEGCLK_W})
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2'b00:
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SB_RAM40_4K #(
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.READ_MODE(READ_MODE),
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.WRITE_MODE(WRITE_MODE),
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.INIT_0(INIT_0),
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.INIT_1(INIT_1),
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.INIT_2(INIT_2),
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.INIT_3(INIT_3),
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.INIT_4(INIT_4),
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.INIT_5(INIT_5),
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.INIT_6(INIT_6),
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.INIT_7(INIT_7),
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.INIT_8(INIT_8),
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.INIT_9(INIT_9),
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.INIT_A(INIT_A),
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.INIT_B(INIT_B),
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.INIT_C(INIT_C),
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.INIT_D(INIT_D),
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.INIT_E(INIT_E),
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.INIT_F(INIT_F)
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) _TECHMAP_REPLACE_ (
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.RDATA(RDATA),
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.RCLK (RCLK ),
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.RCLKE(RCLKE),
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.RE (RE ),
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.RADDR(RADDR),
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.WCLK (WCLK ),
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.WCLKE(WCLKE),
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.WE (WE ),
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.WADDR(WADDR),
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.MASK (MASK ),
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.WDATA(WDATA)
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);
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2'b01:
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SB_RAM40_4KNW #(
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.READ_MODE(READ_MODE),
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.WRITE_MODE(WRITE_MODE),
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.INIT_0(INIT_0),
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.INIT_1(INIT_1),
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.INIT_2(INIT_2),
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.INIT_3(INIT_3),
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.INIT_4(INIT_4),
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.INIT_5(INIT_5),
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.INIT_6(INIT_6),
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.INIT_7(INIT_7),
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.INIT_8(INIT_8),
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.INIT_9(INIT_9),
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.INIT_A(INIT_A),
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.INIT_B(INIT_B),
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.INIT_C(INIT_C),
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.INIT_D(INIT_D),
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.INIT_E(INIT_E),
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.INIT_F(INIT_F)
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) _TECHMAP_REPLACE_ (
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.RDATA(RDATA),
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.RCLK (RCLK ),
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.RCLKE(RCLKE),
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.RE (RE ),
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.RADDR(RADDR),
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.WCLKN(WCLK ),
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.WCLKE(WCLKE),
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.WE (WE ),
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.WADDR(WADDR),
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.MASK (MASK ),
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.WDATA(WDATA)
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);
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2'b10:
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SB_RAM40_4KNR #(
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.READ_MODE(READ_MODE),
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.WRITE_MODE(WRITE_MODE),
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.INIT_0(INIT_0),
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.INIT_1(INIT_1),
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.INIT_2(INIT_2),
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.INIT_3(INIT_3),
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.INIT_4(INIT_4),
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.INIT_5(INIT_5),
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.INIT_6(INIT_6),
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.INIT_7(INIT_7),
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.INIT_8(INIT_8),
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.INIT_9(INIT_9),
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.INIT_A(INIT_A),
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.INIT_B(INIT_B),
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.INIT_C(INIT_C),
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.INIT_D(INIT_D),
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.INIT_E(INIT_E),
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.INIT_F(INIT_F)
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) _TECHMAP_REPLACE_ (
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.RDATA(RDATA),
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.RCLKN(RCLK ),
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.RCLKE(RCLKE),
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.RE (RE ),
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.RADDR(RADDR),
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.WCLK (WCLK ),
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.WCLKE(WCLKE),
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.WE (WE ),
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.WADDR(WADDR),
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.MASK (MASK ),
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.WDATA(WDATA)
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);
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2'b11:
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SB_RAM40_4KNRNW #(
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.READ_MODE(READ_MODE),
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.WRITE_MODE(WRITE_MODE),
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.INIT_0(INIT_0),
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.INIT_1(INIT_1),
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.INIT_2(INIT_2),
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.INIT_3(INIT_3),
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.INIT_4(INIT_4),
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.INIT_5(INIT_5),
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.INIT_6(INIT_6),
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.INIT_7(INIT_7),
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.INIT_8(INIT_8),
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.INIT_9(INIT_9),
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.INIT_A(INIT_A),
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.INIT_B(INIT_B),
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.INIT_C(INIT_C),
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.INIT_D(INIT_D),
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.INIT_E(INIT_E),
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.INIT_F(INIT_F)
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) _TECHMAP_REPLACE_ (
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.RDATA(RDATA),
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.RCLKN(RCLK ),
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.RCLKE(RCLKE),
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.RE (RE ),
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.RADDR(RADDR),
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.WCLKN(WCLK ),
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.WCLKE(WCLKE),
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.WE (WE ),
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.WADDR(WADDR),
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.MASK (MASK ),
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.WDATA(WDATA)
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);
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endcase
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endgenerate
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endmodule
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module \$__ICE40_RAM4K_M0 (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
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parameter [0:0] CLKPOL2 = 1;
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parameter [0:0] CLKPOL3 = 1;
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parameter [4095:0] INIT = 4096'bx;
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input CLK2;
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input CLK3;
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input [7:0] A1ADDR;
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output [15:0] A1DATA;
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input A1EN;
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input [7:0] B1ADDR;
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input [15:0] B1DATA;
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input [15:0] B1EN;
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wire [10:0] A1ADDR_11 = A1ADDR;
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wire [10:0] B1ADDR_11 = B1ADDR;
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\$__ICE40_RAM4K #(
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.READ_MODE(0),
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.WRITE_MODE(0),
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.NEGCLK_R(!CLKPOL2),
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.NEGCLK_W(!CLKPOL3),
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.INIT_0(INIT[ 0*256 +: 256]),
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.INIT_1(INIT[ 1*256 +: 256]),
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.INIT_2(INIT[ 2*256 +: 256]),
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.INIT_3(INIT[ 3*256 +: 256]),
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.INIT_4(INIT[ 4*256 +: 256]),
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.INIT_5(INIT[ 5*256 +: 256]),
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.INIT_6(INIT[ 6*256 +: 256]),
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.INIT_7(INIT[ 7*256 +: 256]),
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.INIT_8(INIT[ 8*256 +: 256]),
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.INIT_9(INIT[ 9*256 +: 256]),
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.INIT_A(INIT[10*256 +: 256]),
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.INIT_B(INIT[11*256 +: 256]),
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.INIT_C(INIT[12*256 +: 256]),
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.INIT_D(INIT[13*256 +: 256]),
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.INIT_E(INIT[14*256 +: 256]),
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.INIT_F(INIT[15*256 +: 256])
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) _TECHMAP_REPLACE_ (
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.RDATA(A1DATA),
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.RADDR(A1ADDR_11),
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.RCLK(CLK2),
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.RCLKE(A1EN),
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.RE(1'b1),
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.WDATA(B1DATA),
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.WADDR(B1ADDR_11),
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.MASK(~B1EN),
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.WCLK(CLK3),
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.WCLKE(|B1EN),
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.WE(1'b1)
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);
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endmodule
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module \$__ICE40_RAM4K_M123 (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
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parameter CFG_ABITS = 9;
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parameter CFG_DBITS = 8;
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parameter [0:0] CLKPOL2 = 1;
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parameter [0:0] CLKPOL3 = 1;
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parameter [4095:0] INIT = 4096'bx;
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localparam MODE =
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CFG_ABITS == 9 ? 1 :
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CFG_ABITS == 10 ? 2 :
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CFG_ABITS == 11 ? 3 : 'bx;
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input CLK2;
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input CLK3;
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input [CFG_ABITS-1:0] A1ADDR;
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output [CFG_DBITS-1:0] A1DATA;
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input A1EN;
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input [CFG_ABITS-1:0] B1ADDR;
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input [CFG_DBITS-1:0] B1DATA;
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input B1EN;
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wire [10:0] A1ADDR_11 = A1ADDR;
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wire [10:0] B1ADDR_11 = B1ADDR;
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wire [15:0] A1DATA_16, B1DATA_16;
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generate
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if (MODE == 1) begin
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assign A1DATA = {A1DATA_16[14], A1DATA_16[12], A1DATA_16[10], A1DATA_16[ 8],
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A1DATA_16[ 6], A1DATA_16[ 4], A1DATA_16[ 2], A1DATA_16[ 0]};
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assign {B1DATA_16[14], B1DATA_16[12], B1DATA_16[10], B1DATA_16[ 8],
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B1DATA_16[ 6], B1DATA_16[ 4], B1DATA_16[ 2], B1DATA_16[ 0]} = B1DATA;
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`include "brams_init1.vh"
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end
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if (MODE == 2) begin
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assign A1DATA = {A1DATA_16[13], A1DATA_16[9], A1DATA_16[5], A1DATA_16[1]};
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assign {B1DATA_16[13], B1DATA_16[9], B1DATA_16[5], B1DATA_16[1]} = B1DATA;
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`include "brams_init2.vh"
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end
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if (MODE == 3) begin
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assign A1DATA = {A1DATA_16[11], A1DATA_16[3]};
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assign {B1DATA_16[11], B1DATA_16[3]} = B1DATA;
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`include "brams_init3.vh"
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end
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endgenerate
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\$__ICE40_RAM4K #(
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.READ_MODE(MODE),
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.WRITE_MODE(MODE),
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.NEGCLK_R(!CLKPOL2),
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.NEGCLK_W(!CLKPOL3),
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.INIT_0(INIT_0),
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.INIT_1(INIT_1),
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.INIT_2(INIT_2),
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.INIT_3(INIT_3),
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.INIT_4(INIT_4),
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.INIT_5(INIT_5),
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.INIT_6(INIT_6),
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.INIT_7(INIT_7),
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.INIT_8(INIT_8),
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.INIT_9(INIT_9),
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.INIT_A(INIT_A),
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.INIT_B(INIT_B),
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.INIT_C(INIT_C),
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.INIT_D(INIT_D),
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.INIT_E(INIT_E),
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.INIT_F(INIT_F)
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) _TECHMAP_REPLACE_ (
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.RDATA(A1DATA_16),
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.RADDR(A1ADDR_11),
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.RCLK(CLK2),
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.RCLKE(A1EN),
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.RE(1'b1),
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.WDATA(B1DATA_16),
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.WADDR(B1ADDR_11),
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.WCLK(CLK3),
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.WCLKE(|B1EN),
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.WE(1'b1)
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);
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endmodule
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