mirror of https://github.com/YosysHQ/yosys.git
131 lines
3.6 KiB
C++
131 lines
3.6 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct Sf2IobsPass : public Pass {
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Sf2IobsPass() : Pass("sf2_iobs", "SF2: insert IO buffers") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" sf2_iobs [options] [selection]\n");
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log("\n");
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log("Add SF2 I/O buffers to top module IOs as needed.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing sf2_iobs pass (insert IO buffers).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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// if (args[argidx] == "-singleton") {
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// singleton_mode = true;
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// continue;
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// }
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break;
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}
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extra_args(args, argidx, design);
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Module *module = design->top_module();
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if (module == nullptr)
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log_cmd_error("No top module found.\n");
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SigMap sigmap(module);
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pool<SigBit> clk_bits;
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pool<SigBit> handled_io_bits;
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dict<SigBit, SigBit> rewrite_bits;
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vector<pair<Cell*, SigBit>> pad_bits;
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for (auto cell : module->cells())
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{
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if (cell->type == "\\SLE") {
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for (auto bit : sigmap(cell->getPort("\\CLK")))
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clk_bits.insert(bit);
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}
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if (cell->type.in("\\INBUF", "\\OUTBUF", "\\CLKBUF")) {
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for (auto bit : sigmap(cell->getPort("\\PAD")))
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handled_io_bits.insert(bit);
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}
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}
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for (auto wire : vector<Wire*>(module->wires()))
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{
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if (!wire->port_input && !wire->port_output)
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continue;
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for (int index = 0; index < GetSize(wire); index++)
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{
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SigBit bit(wire, index);
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SigBit canonical_bit = sigmap(bit);
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if (handled_io_bits.count(canonical_bit))
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continue;
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if (wire->port_input && wire->port_output)
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log_error("Failed to add buffer for inout port bit %s.\n", log_signal(bit));
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IdString buf_type, buf_port;
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if (wire->port_output) {
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buf_type = "\\OUTBUF";
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buf_port = "\\D";
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} else if (clk_bits.count(canonical_bit)) {
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buf_type = "\\CLKBUF";
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buf_port = "\\Y";
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} else {
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buf_type = "\\INBUF";
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buf_port = "\\Y";
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}
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Cell *c = module->addCell(NEW_ID, buf_type);
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SigBit new_bit = module->addWire(NEW_ID);
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c->setPort(buf_port, new_bit);
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pad_bits.push_back(make_pair(c, bit));
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rewrite_bits[canonical_bit] = new_bit;
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log("Added %s cell %s for port bit %s.\n", log_id(c->type), log_id(c), log_signal(bit));
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}
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}
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auto rewrite_function = [&](SigSpec &s) {
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for (auto &bit : s) {
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SigBit canonical_bit = sigmap(bit);
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if (rewrite_bits.count(canonical_bit))
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bit = rewrite_bits.at(canonical_bit);
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}
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};
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module->rewrite_sigspecs(rewrite_function);
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for (auto &it : pad_bits)
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it.first->setPort("\\PAD", it.second);
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}
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} Sf2IobsPass;
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PRIVATE_NAMESPACE_END
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